Table 11-1 shows the ATCM and BTCM in the Cortex-R5F.

There are several check points for running AUTOSAR on Cortex-R5F.

• ATCM usage: R5 SPL does not enable MCU1_0’s ATCM by default and, hence, if the AutoSAR application is being booted on MCU1_0 core from R5 SPL then ATCM shouldn’t be used in the memory layout.
  • Startup_Code should be placed to BTCM in that case.
• Startup_Code alignment: should be 256 bytes aligned.

Example is shown below:

MEMORY
{
  OCMCRAM_Common : ORIGIN = 0x41C50000 , LENGTH = 0x00004000 /* 48 KiB */
  OCMCRAM_Common_NonCache : ORIGIN = 0x41C54000 , LENGTH = 0x00000400 /* 1024 Byte */
  OCMCRAM_Core0 : ORIGIN = 0x41C54400 , LENGTH = 0x00000800 /* 2048 Byte */
  OCMCRAM_Core1 : ORIGIN = 0x41C54C00 , LENGTH = 0x00000400 /* 1024 Byte */
  OCMCRAM_Core2 : ORIGIN = 0x41C55000 , LENGTH = 0x00000400 /* 1024 Byte */
  OCMCRAM_Core3 : ORIGIN = 0x41C55400 , LENGTH = 0x00000400 /* 1024 Byte */
  OCMCRAM_Core4 : ORIGIN = 0x41C55800 , LENGTH = 0x00000400 /* 1024 Byte */
  OCMCRAM_Core5 : ORIGIN = 0x41010000 , LENGTH = 0x00000400 /* 1024 Byte */
  DDR0 : ORIGIN = 0x41C55C00 , LENGTH = 0xA5000 /* 16 MiB */
}

  .Startup_Code : ALIGN(256)
  {
    _Startup_Code_START = .;
    *(.brsStartup)
    . = ALIGN(256);
    _Startup_Code_END = . - 1;
    _Startup_Code_LIMIT = .;
  } > OCMCRAM_Core5