The registration of this interrupt is shown in Section 5.7.2.

/* user_main_nav_high_priority */
ISR(Sciserver_tirtosUserMsgHwiFxn2)
{
    Sciserver_hwiData *uhd = NULL;
    int32_t ret = CSL_PASS;
    bool soft_error = false;

    uhd =   &sciserver_hwi_list[USER_MAIN_NAV_HIGH];

    /* TI RTOS: Osal_DisableInterrupt(0, (int32_t) uhd->irq_num); */
    *(volatile unsigned int *)(0x40F80000 + 0x400 +
        (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_NAVSS0_INTR_ROUTER_0_OUTL_INTR_7/32)*0x20 + 0x0C) = 0x80;

    ret = Sciserver_interruptHandler(uhd, &soft_error);

    if ((ret != CSL_PASS) && (soft_error == true))
    {
        /* TI RTOS: Osal_EnableInterrupt(0, (int32_t) uhd->irq_num); */
        *(volatile unsigned int *)(0x40F80000 + 0x400 +
            (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_NAVSS0_INTR_ROUTER_0_OUTL_INTR_7/32)*0x20 + 0x08) = 0x80;
    }
    else
    {
        /* TI RTOS: (void) SemaphoreP_post(gSciserverUserSemHandles[uhd->semaphore_id]); */
        (void)SetEvent(SciServerHighOsTask,
            Rte_Ev_Run_CtApSciserverHigh_CtApSciserverHighRunnable_SciserverTrigger_UserHi_Trigger);
    }

    /* TI RTOS: Osal_ClearInterrupt(0, (int32_t) uhd->irq_num); */
    *(volatile unsigned int *)(0x40F80000 + 0x400 +
        (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_NAVSS0_INTR_ROUTER_0_OUTL_INTR_7/32)*0x20 + 0x04) = 0x80;

}