SPRACY6
July 2021
DRA821U
,
DRA821U-Q1
,
DRA829J
,
DRA829V
,
DRA829V-Q1
,
TDA4VM
,
TDA4VM-Q1
Trademarks
1
Introduction
1.1
SYSFW
1.2
TISCI
1.3
TISCI Client or SciClient
1.4
TISCI Server or SciServer
1.5
Acronyms Used in This Document
2
Target Audience
3
MCU1_0 Role in Jacinto7 SDK V7.1+
4
TISCI Client and Server on TI-RTOS
4.1
J7 SDK Download
4.2
SciClient Driver Location
4.3
TISCI Server Initialization Example
4.4
Integration Guide
4.4.1
Semaphore
4.4.2
Interrupts Registration
4.4.3
Interrupts Handling
4.4.4
User Tasks Registration
4.4.5
User Tasks Processing
5
Configurations in DaVinci
5.1
DaVinci Developer
5.2
DaVinci Configurator Pro
5.3
Resource
5.4
Events
5.4.1
Event for High Priority Requests
5.4.2
Event for Normal Priority Requests
5.5
SciServer User Tasks
5.5.1
High Priority User Task
5.5.2
Normal Priority UserTask
5.6
Synchronization Between Sciserver User Tasks
5.6.1
Configure the Resource for High Priority User Task
5.6.2
Configure the Resource for Normal Priority User Task
5.7
Sciserver Interrupts
5.7.1
MCU Domain Navigation System High Priority Interrupts
5.7.2
Main Domain Navigation System High Priority Interrupts
5.7.3
MCU Domain Navigation System Normal Priority Interrupts
5.7.4
Main Domain Navigation System Normal Priority Interrupts
6
AUTOSAR TISCI Client
6.1
TISCI Client Registration in AUTOSAR
7
AUTOSAR TISCI Interrupts Handling
7.1
MCU Domain Navigation System High Priority Interrupts
7.2
Main Domain Navigation System High Priority Interrupts
7.3
MCU Domain Navigation System Normal Priority Interrupts
7.4
Main Domain Navigation System Normal Priority Interrupts
8
AUTOSAR TISCI User Tasks Processing
8.1
High Priority User Task Initialization
8.2
High Priority User Task Runnable
8.3
Normal Priority User Task Initialization
8.4
Normal Priority User Task Runnable
9
TISCI Server Validation in AUTOSAR
9.1
Boot App
9.2
Boot Task Configuration
9.3
Boot App in AUTOSAR
9.3.1
Boot App Launch
9.3.2
Boot App Implementation
10
PDK Libraries Used in AUTOSAR
11
R5F Configurations Needed for AUTOSAR
11.1
Memory Layout for Cortex-R5F
11.2
R5F Cache Configuration
1
Introduction