SPRAD12A July   2022  – February 2023 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P550SJ , TMS320F28P559SJ-Q1 , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 SysConfig
  5. 3 Time-Base (TB) Submodule
    1. 3.1 Setting the Frequency
    2. 3.2 Applying a Phase Shift
    3. 3.3 Setting up the Synchronization (Sync) Scheme
  6. 4 Counter-Compare (CC) and Action-Qualifier (AQ) Submodules
    1. 4.1 Calculating the Duty Cycle
  7. 5 Deadband (DB) Submodule
    1. 5.1 Setting up Signal Pairs
  8. 6 Verifying the Output
    1. 6.1 Checking the Duty Cycle and Dead-Time Insertion
    2. 6.2 Checking the Phase Shift Applied
  9. 7 Trip-Zone (TZ) and Digital Compare (DC) Submodules
    1. 7.1 Drive Outputs Low for an ePWM Cycle Upon Trip Condition Set Through CMPSS
    2. 7.2 Drive Outputs Low Until Cleared Through Software Upon Trip Condition set Through GPIO
  10. 8 Event-Trigger (ET) Submodule
    1. 8.1 Setting Up Time-Base Interrupts
  11. 9 Global Load
    1. 9.1 Applying Global Loading and One-Shot Load Feature
    2. 9.2 Linking the ePWM Modules
    3. 9.3 Updating Action Qualifier Settings and Counter Compare Values Through Global Loading
  12. 10Summary
  13. 11References
  14. 12Revision History

6.2 Checking the Phase Shift Applied

The three ePWM outputs are phase shifted. EPWM2 has a 120° phase shift with respect to EPWM1, and EPWM3 has a 240° phase shift with respect to EPWM1. As seen from GUID-363DB621-E359-40E8-A6D8-9ADA34EA7B45.html#GUID-DBF27521-E746-41C7-B62D-D24FB6D8B3BD and GUID-363DB621-E359-40E8-A6D8-9ADA34EA7B45.html#GUID-B1E167D7-8210-4DB3-A535-B1CD0A28FFE5, TBPHS is set to 42 for EPWM2 and 83 for EPWM3. Based on the synchronization scheme that was set up, every time EPWM1’s time-base counter is equal to 0, a synchronization pulse is generated in which the time-base counter of EPWM2 and EPWM3 is set to the value in the TBPHS register.

Note: The delay from the internal synchronization source module to a synchronization receive module is given by 2 x EPWMCLK if TBCLK = EPWMCLK.

Based on the note, EPWM2 and EPWM3's time-base counter is not set to the TBPHS value, but rather TBPHS + 2. For example, for EPWM2, the TBPHS is 42 counts, which means 42 * 10 nsec = 420 nsec, but accounting for the additional cycles, this is 2 * 10 nsec = 20 nsec, 440 nsec in total. #GUID-32101E24-2DAE-4546-B15D-8CA1ECEC22D7 shows the time delay between the rising edge of EPWM1A and EPWM2A to showcase the phase difference.

Figure 6-3 Scope Capture of the EPWM Output With Phase Shift