SPRAD59 October   2023 TMS320F280039

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Key Differences Between DCAN and MCAN
  6. 3 Module Initialization
    1. 3.1 DCAN Initialization
    2. 3.2 MCAN Initialization
    3. 3.3 Initialization sequence
    4. 3.4 Code Snippets for Module Initialization
  7. 4 Bit Timing Configuration
  8. 5 Message RAM Configuration
  9. 6 Interrupt handling
    1. 6.1 MCAN Interrupt Sources
    2. 6.2 DCAN Interrupt Handling
    3. 6.3 MCAN Interrupt Handling
  10. 7 Transmitting data
    1. 7.1 Basic Transmission Process
      1. 7.1.1 Transmission with DCAN
      2. 7.1.2 Transmission with MCAN
    2. 7.2 MCAN Vs DCAN Transmit Procedural Differences
    3. 7.3 MCAN Transmit Concepts
      1. 7.3.1 Tx Event FIFO
  11. 8 Receiving Data
    1. 8.1 Introduction to Reception
    2. 8.2 Basic Reception Process
      1. 8.2.1 DCAN Reception
      2. 8.2.2 MCAN Reception
    3. 8.3 Filter Elements
      1. 8.3.1 Filter Element Structure
    4. 8.4 Rx Buffer
      1. 8.4.1 Receiving in Rx Buffer
    5. 8.5 Rx FIFO
      1. 8.5.1 Receiving in Rx FIFO
    6. 8.6 Receiving High Priority Messages
  12. 9 Avoiding network errors
  13. 10References

4 Bit Timing Configuration

Bit timing configuration differs between classic CAN and CAN FD. The process is relatively easier in classic CAN, since the bit-rate is the same for the entire frame. However, in CAN FD, two different bit-rates can be used: a slower “nominal” bit-rate and a faster “data” bit-rate. In the MCAN module, these two bit-rates are configured by writing to the MCAN_NBTP and MCAN_DBTP registers respectively during the module initialization. Note that an application can choose to only take advantage of the higher number of data bytes per frame that can be transmitted in CAN FD and use the same bit-rate for the entire frame. The faster bit-rate for the data phase also warrants Transmitter Delay Compensation (TDC) without which bit errors can occur. Below is an example for calculating bit-timing parameters:

Example 1

Assume the following parameters are desired with a CAN module clock of 200 MHz:

Nominal bit-rate = 500kbps, Data bit-rate = 2Mbps.

The formula for computing the bit-rate is given by:

Equation 1. Bit-rate=CAN module clockBit-rate prescaler ×Bit-time

For a nominal bit-rate of 500kbps, the product of Bit-rate prescaler x Bit-time must be equal to 400. This can be achieved with multiple combinations of the prescaler and bit-time, as long as the rules laid out by the CAN protocol are not violated. For example, a prescaler of 20 and a bit-time of 20 TQ can be chosen. A prescaler of 20 (NBRPreg = 19) yields a bit-clock of 10 MHz with a resultant time-quanta (TQ) of 100 ns. A bit-time of 20 TQ can be achieved with multiple combinations for TSEG1 and TSEG2 resulting in varying sample-points (SP).

Bit-time = (NTSEG1reg + 1) + (NTSEG2reg + 1) + 1, where NTSEG1reg and NTSEG2reg represent the actual values written into MCAN_NBTP.NTSEG1 and MCAN_NBTP.NTSEG2 bit-fields respectively. If TSEG1 is chosen to be 16 (NTSEG1reg = 15) and TSEG2 is chosen to be 4 (NTSEG2reg =3), those values yield a sampling-point of 80%. By adjusting the TSEG1 and TSEG2 values, the sampling-point can be moved within the bit-time based on the network parameters.

Similar calculation is used for data bit-rate of 2Mbps. For a data bit-rate of 2Mbps, the product of Bit-rate prescaler x Bit-time must be equal to 100. This can be achieved with multiple combinations of the prescaler and bit-time, as long as the rules laid out by the CAN protocol are not violated. For example, a prescaler of 5 and a bit-time of 20 TQ can be chosen. A prescaler of 5 (DBRPreg = 4) yields a bit-clock of 40 MHz with a resultant time-quanta (TQ) of 25ns. A bit-time of 20 TQ can be achieved with multiple combinations for TSEG1 and TSEG2 resulting in varying sample-points (SP).

Bit-time = (DTSEG1reg + 1) + (DTSEG2reg + 1) + 1, where DTSEG1reg and DTSEG1reg represent the actual values written into MCAN_DBTP.DTSEG1 and MCAN_DBTP.DTSEG2 bit-fields respectively. If TSEG1 is chosen to be 16 (DTSEG1reg = 15) and TSEG2 is chosen to be 4 (NTSEG2reg =3), those values yield a sampling-point of 80%. By adjusting the TSEG1 and TSEG2 values, the sampling-point can be moved within the bit-time based on the network parameters.

GUID-20231010-SS0I-JDWM-P0MF-NXTTHQ6NP2XH-low.png Figure 4-1 MCAN Bit-timing Configuration