SPRAD59 October   2023 TMS320F280039

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Key Differences Between DCAN and MCAN
  6. 3 Module Initialization
    1. 3.1 DCAN Initialization
    2. 3.2 MCAN Initialization
    3. 3.3 Initialization sequence
    4. 3.4 Code Snippets for Module Initialization
  7. 4 Bit Timing Configuration
  8. 5 Message RAM Configuration
  9. 6 Interrupt handling
    1. 6.1 MCAN Interrupt Sources
    2. 6.2 DCAN Interrupt Handling
    3. 6.3 MCAN Interrupt Handling
  10. 7 Transmitting data
    1. 7.1 Basic Transmission Process
      1. 7.1.1 Transmission with DCAN
      2. 7.1.2 Transmission with MCAN
    2. 7.2 MCAN Vs DCAN Transmit Procedural Differences
    3. 7.3 MCAN Transmit Concepts
      1. 7.3.1 Tx Event FIFO
  11. 8 Receiving Data
    1. 8.1 Introduction to Reception
    2. 8.2 Basic Reception Process
      1. 8.2.1 DCAN Reception
      2. 8.2.2 MCAN Reception
    3. 8.3 Filter Elements
      1. 8.3.1 Filter Element Structure
    4. 8.4 Rx Buffer
      1. 8.4.1 Receiving in Rx Buffer
    5. 8.5 Rx FIFO
      1. 8.5.1 Receiving in Rx FIFO
    6. 8.6 Receiving High Priority Messages
  12. 9 Avoiding network errors
  13. 10References

3.3 Initialization sequence

The individual steps for initialization of DCAN and MCAN modules, along with the key differences have been listed in Table 3-1:

Table 3-1 DCAN/MCAN Initialization Sequence
OperationDCANMCAN
Enter Initialization ModeSet CAN_CTL.INIT bitSet MCAN_CCCR.INIT bit and check that the bit has been set
Unlock Protected RegistersSet CAN_CTL.CCE bitSet MCAN_CCCR.CCE bit
Configure CAN Mode and Bit Rate SwitchingNot applicableSet MCAN_CCCR.FDOE bit for CAN FD function

Set MCAN_CCCR.BRSE bit to enable Bit Rate Switching (BRS)

(Both bits need to be 0 for Classic CAN Communication)
Configure bit-timingConfigure CAN_BTR registerConfigure MCAN_NBTP register
Configure data bit-timingNot applicableConfigure MCAN_DBTP register (Not needed for Classic CAN as BRS is disabled)
Message RAM ConfigurationNot applicableSee Message RAM configuration
Global Filter Configuration, if required (determines how the module handles non-matching frames).Not applicableSet MCAN_GFC Register
Receive and Transmit Configuration (can be done at run time as well)Setup Message ObjectFilter Configuration
Lock Protected RegistersClear CAN_CTL.CCE bitClear MCAN_CCCR.CCE bit
Return module to normal operationClear CAN_CTL.INIT bitClear MCAN_CCCR.INIT bit

In addition to the steps shown above, for MCAN, the MCAN Clock Divider may need to be set up as part of the initialization process. This configuration is typically done via the AUXCLKDIVSEL register (refer to the device-specific TRM to determine the register for clock division). For 120 MHz and 200 MHz devices, C2000ware examples configure the MCAN bit-clock to 40 MHz. If an application desires a smaller time quanta (TQ), other configurations for the bit-clock are possible. However, the parameters for the Nominal and Data Bit Timings need to be changed accordingly. Figure 3-1 shows the initialization steps for DCAN. Figure 3-2, Figure 3-3, and Figure 3-4 show the initialization steps for MCAN.