SPRAD59 October   2023 TMS320F280039

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Key Differences Between DCAN and MCAN
  6. 3 Module Initialization
    1. 3.1 DCAN Initialization
    2. 3.2 MCAN Initialization
    3. 3.3 Initialization sequence
    4. 3.4 Code Snippets for Module Initialization
  7. 4 Bit Timing Configuration
  8. 5 Message RAM Configuration
  9. 6 Interrupt handling
    1. 6.1 MCAN Interrupt Sources
    2. 6.2 DCAN Interrupt Handling
    3. 6.3 MCAN Interrupt Handling
  10. 7 Transmitting data
    1. 7.1 Basic Transmission Process
      1. 7.1.1 Transmission with DCAN
      2. 7.1.2 Transmission with MCAN
    2. 7.2 MCAN Vs DCAN Transmit Procedural Differences
    3. 7.3 MCAN Transmit Concepts
      1. 7.3.1 Tx Event FIFO
  11. 8 Receiving Data
    1. 8.1 Introduction to Reception
    2. 8.2 Basic Reception Process
      1. 8.2.1 DCAN Reception
      2. 8.2.2 MCAN Reception
    3. 8.3 Filter Elements
      1. 8.3.1 Filter Element Structure
    4. 8.4 Rx Buffer
      1. 8.4.1 Receiving in Rx Buffer
    5. 8.5 Rx FIFO
      1. 8.5.1 Receiving in Rx FIFO
    6. 8.6 Receiving High Priority Messages
  12. 9 Avoiding network errors
  13. 10References

6 Interrupt handling

From a CPU level (PIE, IFR and INTM), interrupt handling is identical between DCAN and MCAN. However, interrupt handling differs significantly at the module level. Table 6-1 summarizes the basic differences in interrupt handling between DCAN and MCAN modules:

Table 6-1 Interrupt Handling in DCAN and MCAN
Category DCAN MCAN
Interrupt sourcesError, Status and Transmission/Reception interrupts corresponding to each message object30 internal interrupt sources (specified in table below )
Global interrupt registersRegisters to enable, read and clear global interrupts presentCorresponding register is absent
Configuring reception interruptReception interrupt can be separately enabled by setting RxIE bit in each Message Object as requiredInterrupt can be enabled or disabled for any new message being received in dedicated Rx Buffer.
Determining source of receive interruptValue read from register CAN_INT corresponds to Message Object Number where message has been received inInterrupt only denotes that a new message has been received in Rx Buffer. Value read from MCAN_NDATx registers corresponds to Rx Buffer element number where message has been received.
Rx FIFO interruptsNo separate interrupt functionality supportedAdditional interrupt sources available including New Message in FIFO, FIFO being full and FIFO Watermark Reached (Watermark can be configured during Message RAM configuration to generate an interrupt when FIFO is filled to a certain level to serve the application needs)
Configuring transmission interruptsTransmission interrupt can be separately enabled by setting TxIE bit in each Message Object as requiredTransmission interrupt can be separately enabled by configuring the register MCAN_TXBTIE, where each bit corresponds to a separate Tx Buffer Element.
Determining Source of transmission interruptValue read from register CAN_INT corresponds to Message Object Number where message has been transmitted fromInterrupt only denotes that a transmission has been completed. Value read from the MCAN_TXBTO register corresponds to the Tx Buffer element number from which the transmission has occurred.