SPRAD61A
March 2023 – November 2023
AM2732
,
AM2732
,
AM2732-Q1
,
AM2732-Q1
1
Abstract
Trademarks
1
Introduction
1.1
Acronyms
2
Power
2.1
Discrete DC-DC Power Solution
2.2
Integrated PMIC Power Solution
2.3
Power Decoupling and Filtering
2.4
Power Consumption
3
Clocking
3.1
Crystal and Oscillator Input Options
3.2
Output Clock Generation
3.3
Crystal Selection and Shunt Capacitance
3.4
Crystal Placement and Routing
4
Resets
5
Bootstrapping
5.1
SOP Signal Implementation
5.2
QSPI Memory Controller Implementation
5.3
ROM QSPI Boot Requirements
6
JTAG Emulators and Trace
7
Multiplexed Peripherals
8
Digital Peripherals
8.1
General Digital Peripheral Routing Guidelines
9
Layer Stackup
9.1
TMDS273GPEVM Layer Stackup
9.1.1
TMDS273GPEVM Key Stackup Features
9.2
Four Layer ZCE Example Layer Stackup
9.2.1
ZCE Four Layer Example Key Stackup Features
9.3
Four Layer NZN Example Layer Stackup
9.3.1
NZN Four Layer Example Key Stackup Features
10
Vias
11
BGA Power Fan-Out and Decoupling Placement
11.1
Ground Return
11.1.1
Ground Return - TMDS273GPEVM
11.1.2
Ground Return - ZCE Four Layer Example
11.1.3
Ground Return - NZN Four Layer Example
11.2
1.2 V Core Digital Power
11.2.1
1.2 V Core Digital Power Key Layout Considerations
11.2.1.1
1.2V Core Layout - TMDS273GPEVM
11.2.1.2
1.2V Core Layout - ZCE Four Layer Example
11.2.1.3
1.2V Core Layout - NZN Four Layer Example
11.3
3.3 V Digital and Analog Power
11.3.1
3.3 V Digital and Analog Power Key Layout Considerations
11.3.1.1
3.3V Digital and Analog Layout - TMDS273GPEVM
11.3.1.2
3.3V Digital and Analog Layout - ZCE Four Layer Example
11.3.1.3
3.3V Digital and Analog Layout - NZN Four Layer Example
11.4
1.8 V Digital and Analog Power
11.4.1
1.8 V Digital and Analog Power Key Layout Considerations
11.4.1.1
1.8V Digital and Analog Layout - TMDS273GPEVM
11.4.1.2
1.8V Digital and Analog Layout - ZCE Four Layer Example
11.4.1.3
1.8V Digital and Analog Layout - NZN Four Layer Example
12
References
13
Revision History
2
Power