SPRAD61A March   2023  – November 2023 AM2732 , AM2732 , AM2732-Q1 , AM2732-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 QSPI Memory Controller Implementation
    3. 5.3 ROM QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Layer Stackup
    1. 9.1 TMDS273GPEVM Layer Stackup
      1. 9.1.1 TMDS273GPEVM Key Stackup Features
    2. 9.2 Four Layer ZCE Example Layer Stackup
      1. 9.2.1 ZCE Four Layer Example Key Stackup Features
    3. 9.3 Four Layer NZN Example Layer Stackup
      1. 9.3.1 NZN Four Layer Example Key Stackup Features
  13. 10Vias
  14. 11BGA Power Fan-Out and Decoupling Placement
    1. 11.1 Ground Return
      1. 11.1.1 Ground Return - TMDS273GPEVM
      2. 11.1.2 Ground Return - ZCE Four Layer Example
      3. 11.1.3 Ground Return - NZN Four Layer Example
    2. 11.2 1.2 V Core Digital Power
      1. 11.2.1 1.2 V Core Digital Power Key Layout Considerations
        1. 11.2.1.1 1.2V Core Layout - TMDS273GPEVM
        2. 11.2.1.2 1.2V Core Layout - ZCE Four Layer Example
        3. 11.2.1.3 1.2V Core Layout - NZN Four Layer Example
    3. 11.3 3.3 V Digital and Analog Power
      1. 11.3.1 3.3 V Digital and Analog Power Key Layout Considerations
        1. 11.3.1.1 3.3V Digital and Analog Layout - TMDS273GPEVM
        2. 11.3.1.2 3.3V Digital and Analog Layout - ZCE Four Layer Example
        3. 11.3.1.3 3.3V Digital and Analog Layout - NZN Four Layer Example
    4. 11.4 1.8 V Digital and Analog Power
      1. 11.4.1 1.8 V Digital and Analog Power Key Layout Considerations
        1. 11.4.1.1 1.8V Digital and Analog Layout - TMDS273GPEVM
        2. 11.4.1.2 1.8V Digital and Analog Layout - ZCE Four Layer Example
        3. 11.4.1.3 1.8V Digital and Analog Layout - NZN Four Layer Example
  15. 12References
  16. 13Revision History

5.2 QSPI Memory Controller Implementation

The QSPI memory is the primary boot memory location for the AM273x MCU. Good signal integrity of this memory interface is critical for basic QSPI boot operations of the AM273x MCU. Additional pull-up resistors are also necessary.

  • Include a chip-select pull-up resistor to ensure that the device is normally read/write disabled until the AM273x QSPI controller drives chip-select low at the start of a new read/write transaction.
  • Include a pull resistor to disable write protect mode by default
  • Include a pull resistor to disable hold mode by default
GUID-F5DFD41C-2564-42CA-B0E4-D2EE4CA12F67-low.png Figure 5-2 Excerpt From AM273x GPEVM Schematic – AM273x QSPI Controller and GD25B64CWAG NOR Flash Memory

Additional routing guidelines for the QSPI memory interface are provided in Figure 5-3 and Table 5-2 These should be used as maximum routing and skew match limits.

GUID-1D118455-DD6C-4943-941F-A22E06892205-low.svg Figure 5-3 AM273x QSPI - Routing Rules Diagram
Table 5-2 AM273x QSPI – Recommended Routing Rules
Spec No. Specification Value Unit
1 QSPI_CLK, QSPI_CS0, QSPI_D[3:0] maximum delay 450 ps
2 QSPI_CLK to QSPI_D[3:0] maximum skew 50 ps
3 Approximate maximum routing distances 3214 mils
4 Approximate maximum routing skew 357 mils
5 A series termination resistor (R1 in diagram above) should be placed close to the QSPI_CLK transmit pin of the AM273x to control rise-time and reflections of the clock line. Variable, 0 to 40 Ω
6 A series termination resistor (R2 in diagram above) should be placed close to the QSPI data pins of the attached memory to control rise-time and reflections of the data lines. Variable, 0 to 40 Ω
Note: Approximate routing distances computed assuming a typical 140 ps/inch propagation delay in 50-Ω FR4 Microstrip or Stripline transmission lines. A 2D field solver or appropriate closed-form approximate impedance equations should be used to find more exact propagation delay for a specific given stackup and routing.

It is recommended that the QSPI memory be co-located close to the AM273x BGA footprint, which allows for routing that maximizes the delay margins and skew margins. As seen in Figure 5-3 it is also recommended to include a series termination resistor near the QSPI controller clock transmit pin. Similarly, series terminations should be added at the data pins of the QSPI device as well. During read quad-read operations, which will be the most used mode of operation of the memory, this helps create well controlled edges on the data lines.