SPRAD61A March   2023  – November 2023 AM2732 , AM2732 , AM2732-Q1 , AM2732-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 QSPI Memory Controller Implementation
    3. 5.3 ROM QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Layer Stackup
    1. 9.1 TMDS273GPEVM Layer Stackup
      1. 9.1.1 TMDS273GPEVM Key Stackup Features
    2. 9.2 Four Layer ZCE Example Layer Stackup
      1. 9.2.1 ZCE Four Layer Example Key Stackup Features
    3. 9.3 Four Layer NZN Example Layer Stackup
      1. 9.3.1 NZN Four Layer Example Key Stackup Features
  13. 10Vias
  14. 11BGA Power Fan-Out and Decoupling Placement
    1. 11.1 Ground Return
      1. 11.1.1 Ground Return - TMDS273GPEVM
      2. 11.1.2 Ground Return - ZCE Four Layer Example
      3. 11.1.3 Ground Return - NZN Four Layer Example
    2. 11.2 1.2 V Core Digital Power
      1. 11.2.1 1.2 V Core Digital Power Key Layout Considerations
        1. 11.2.1.1 1.2V Core Layout - TMDS273GPEVM
        2. 11.2.1.2 1.2V Core Layout - ZCE Four Layer Example
        3. 11.2.1.3 1.2V Core Layout - NZN Four Layer Example
    3. 11.3 3.3 V Digital and Analog Power
      1. 11.3.1 3.3 V Digital and Analog Power Key Layout Considerations
        1. 11.3.1.1 3.3V Digital and Analog Layout - TMDS273GPEVM
        2. 11.3.1.2 3.3V Digital and Analog Layout - ZCE Four Layer Example
        3. 11.3.1.3 3.3V Digital and Analog Layout - NZN Four Layer Example
    4. 11.4 1.8 V Digital and Analog Power
      1. 11.4.1 1.8 V Digital and Analog Power Key Layout Considerations
        1. 11.4.1.1 1.8V Digital and Analog Layout - TMDS273GPEVM
        2. 11.4.1.2 1.8V Digital and Analog Layout - ZCE Four Layer Example
        3. 11.4.1.3 1.8V Digital and Analog Layout - NZN Four Layer Example
  15. 12References
  16. 13Revision History

3.1 Crystal and Oscillator Input Options

The AM273x primary clock interface, CLKM and CLKP (ZCE pins U1 and V1, NZN pins N1 and P2), can be sourced from either an attached crystal or a single-ended oscillator output. The attached crystal should be a fundamental mode crystal operating at 40 MHz. If operating from a single-ended oscillator output, the CLKP pin should be connected to the oscillator and the CLKM pin must be connected to ground. In oscillator input mode, the CLKP pin can be tied to either a 1.8 V DC-coupled square wave or AC-coupled sine wave oscillator. For full crystal and oscillator input requirements, see the AM273x Sitara™ Microcontroller Data Sheet.

GUID-361526F0-20CB-4C59-9B24-FC2033DB6E1F-low.png Figure 3-1 Excerpt From AM273x GPEVM Schematics

Additional clock inputs for the AM273x include:

  • Two external reference clock inputs, XREF_CLK0 and XREF_CLK1 (ZCE pins J1 and K2, NZN pins G1 and G2), that can be used as dedicated peripheral clock sources for system synchronization.
  • Two Camera Subsystem 2.0 (CSI2.0) Clock inputs, CSI2_RX0CLKM/CSI2_RX0CLKP (ZCE pins B6 and A6) for CSI2.0 Receiver #1 and CSI2_RX1CLKM/CSI2_RX1CLKP (ZCE pins A11 and B11) for CSI2.0 Receiver #2.