SPRAD61A March   2023  – November 2023 AM2732 , AM2732 , AM2732-Q1 , AM2732-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 QSPI Memory Controller Implementation
    3. 5.3 ROM QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Layer Stackup
    1. 9.1 TMDS273GPEVM Layer Stackup
      1. 9.1.1 TMDS273GPEVM Key Stackup Features
    2. 9.2 Four Layer ZCE Example Layer Stackup
      1. 9.2.1 ZCE Four Layer Example Key Stackup Features
    3. 9.3 Four Layer NZN Example Layer Stackup
      1. 9.3.1 NZN Four Layer Example Key Stackup Features
  13. 10Vias
  14. 11BGA Power Fan-Out and Decoupling Placement
    1. 11.1 Ground Return
      1. 11.1.1 Ground Return - TMDS273GPEVM
      2. 11.1.2 Ground Return - ZCE Four Layer Example
      3. 11.1.3 Ground Return - NZN Four Layer Example
    2. 11.2 1.2 V Core Digital Power
      1. 11.2.1 1.2 V Core Digital Power Key Layout Considerations
        1. 11.2.1.1 1.2V Core Layout - TMDS273GPEVM
        2. 11.2.1.2 1.2V Core Layout - ZCE Four Layer Example
        3. 11.2.1.3 1.2V Core Layout - NZN Four Layer Example
    3. 11.3 3.3 V Digital and Analog Power
      1. 11.3.1 3.3 V Digital and Analog Power Key Layout Considerations
        1. 11.3.1.1 3.3V Digital and Analog Layout - TMDS273GPEVM
        2. 11.3.1.2 3.3V Digital and Analog Layout - ZCE Four Layer Example
        3. 11.3.1.3 3.3V Digital and Analog Layout - NZN Four Layer Example
    4. 11.4 1.8 V Digital and Analog Power
      1. 11.4.1 1.8 V Digital and Analog Power Key Layout Considerations
        1. 11.4.1.1 1.8V Digital and Analog Layout - TMDS273GPEVM
        2. 11.4.1.2 1.8V Digital and Analog Layout - ZCE Four Layer Example
        3. 11.4.1.3 1.8V Digital and Analog Layout - NZN Four Layer Example
  15. 12References
  16. 13Revision History

5.1 SOP Signal Implementation

Each SOP[n] signal is multiplexed with different peripheral functional mode signals as well. For more information, see the signal description tables in the AM273x Sitara™ Microcontroller Data Sheet. The SOP signal descriptions are excerpted below.

Table 5-1 SOP and Functional Mode Signal Mapping
Pin Number - ZCE Pin Number - NZN Primary Pinmux Signal SOP Mode Signal
D6 C6 TDO SOP[0]
E17 C14 MSS_MIBSPIB_CS2 SOP[1]
F1 D3 PMIC_CLKOUT SOP[2]
V9 P4 MSS_UARTB_TX SOP[3]
W2 R4 MSS_UARTA_TX SOP[4]

Because of this SOP/functional-mode multiplexing additional care must be taken in schematic and layout to ensure that the SOP mode selection resistors, jumpers or switch paths are routed in such a way that the SOP mode branches do not present inductive stubs to the functional mode signal paths. Failing to take care of this may result in non-functional interfaces during normal operation.

GUID-F624CDE2-CB4F-4196-9F34-778ED78848F2-low.png Figure 5-1 Excerpt From AM273x GPEVM Schematic – SOP[4:0] Functional and SOP Paths

In the AM273x GPEVM design this SOP mode isolation is accomplished by including a 10KΩ resistor in the SOP signal path for SOP[2:0]. For SOP[4:3], the 10KΩ pulldown resistor setting the SOP bit to 0 does not impact the function of the UART TX lines, so no isolating 10KΩ resistor is necessary. Ideally, the resistor is placed such as one pad is as close to the AM273x BGA pad and in-line with the functional mode path. This creates a layout where the additional stub length necessary to breakout the SOP path will only minimally impact the functional mode operation of the signals.