SPRAD61A March   2023  – November 2023 AM2732 , AM2732 , AM2732-Q1 , AM2732-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 QSPI Memory Controller Implementation
    3. 5.3 ROM QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Layer Stackup
    1. 9.1 TMDS273GPEVM Layer Stackup
      1. 9.1.1 TMDS273GPEVM Key Stackup Features
    2. 9.2 Four Layer ZCE Example Layer Stackup
      1. 9.2.1 ZCE Four Layer Example Key Stackup Features
    3. 9.3 Four Layer NZN Example Layer Stackup
      1. 9.3.1 NZN Four Layer Example Key Stackup Features
  13. 10Vias
  14. 11BGA Power Fan-Out and Decoupling Placement
    1. 11.1 Ground Return
      1. 11.1.1 Ground Return - TMDS273GPEVM
      2. 11.1.2 Ground Return - ZCE Four Layer Example
      3. 11.1.3 Ground Return - NZN Four Layer Example
    2. 11.2 1.2 V Core Digital Power
      1. 11.2.1 1.2 V Core Digital Power Key Layout Considerations
        1. 11.2.1.1 1.2V Core Layout - TMDS273GPEVM
        2. 11.2.1.2 1.2V Core Layout - ZCE Four Layer Example
        3. 11.2.1.3 1.2V Core Layout - NZN Four Layer Example
    3. 11.3 3.3 V Digital and Analog Power
      1. 11.3.1 3.3 V Digital and Analog Power Key Layout Considerations
        1. 11.3.1.1 3.3V Digital and Analog Layout - TMDS273GPEVM
        2. 11.3.1.2 3.3V Digital and Analog Layout - ZCE Four Layer Example
        3. 11.3.1.3 3.3V Digital and Analog Layout - NZN Four Layer Example
    4. 11.4 1.8 V Digital and Analog Power
      1. 11.4.1 1.8 V Digital and Analog Power Key Layout Considerations
        1. 11.4.1.1 1.8V Digital and Analog Layout - TMDS273GPEVM
        2. 11.4.1.2 1.8V Digital and Analog Layout - ZCE Four Layer Example
        3. 11.4.1.3 1.8V Digital and Analog Layout - NZN Four Layer Example
  15. 12References
  16. 13Revision History

2.3 Power Decoupling and Filtering

Table 2-1 describes the initial BGA decoupling and power filtering required for the AM273x. These were based on the initial simulation feedback of the AM273 GPEVM PCB and AM273x package with the above transient use-cases.

The decoupling network presented in the below sections and in the AM273x EVM schematics and layouts are reasonable starting points for any AM273x PCB design. Additional placement guidance for the decoupling network is provided in Section 11. However, due to specific PCB routing differences and the resulting plane capacitance and decoupling mounting inductances and other parasitics, it is highly recommended that designers simulate and measure their specific power distribution network performance. Simulations and measurements should ideally be done with target application software active and intended operating environment conditions applied to the system.

Table 2-1 AM273x Recommended Decoupling per Power Net
Device Supply Quantity Comment Part Number Manufacturer
1.2-V VDD_CORE 2 2.2 µF, 6.3 V, ± 10%, X7R, AEC-Q200 Grade 1, 0603 GCM188R70J225KE22D Murata
5 0.22 µF, 16 V,± 10%, X7R, AEC-Q200 Grade 1, 0402 GCM155R71C224KE02D Murata
3 0.01 µF, 50 V, ± 10%, X7R, AEC-Q200 Grade 1, 0402 CGA2B3X7R1H103K050BB TDK
1.2-V SRAM 1 0.22 µF, 16 V, ± 10%, X7R, AEC-Q200 Grade 1, 0402 GCM155R71C224KE02D Murata
2 0.1 µF, 16 V, ± 10%, X7R, 0402 GCM155R71C104KA55D Murata
1.8-V IO Supply 4 0.22 µF, 16 V, ± 10%, X7R, AEC-Q200 Grade 1, 0402 GCM155R71C224KE02D Murata
3.3-V IO Supply 1 2.2 µF, 6.3 V, ± 10%, X7R, AEC-Q200 Grade 1, 0603 GCM188R70J225KE22D Murata
6 0.22 µF, 16 V, ± 10%, X7R, AEC-Q200 Grade 1, 0402 GCM155R71C224KE02D Murata
1.8-V ADC Supply 1 0.22 µF, 16 V, ± 10%, X7R, AEC-Q200 Grade 1, 0402 GCM155R71C224KE02D Murata
1.8-V Clock Supply 1 0.22 µF, 16 V, ± 10%, X7R, AEC-Q200 Grade 1, 0402 GCM155R71C224KE02D Murata
1.8-V CSI Supply 1 0.22 µF, 16 V, ± 10%, X7R, AEC-Q200 Grade 1, 0402 GCM155R71C224KE02D Murata
1.8-V LVDS Supply 1 0.22 µF, 16 V, ± 10%, X7R, AEC-Q200 Grade 1, 0402 GCM155R71C224KE02D Murata
VNWA Supply 1 0.1 µF, 16 V, ± 10%, X7R, 0402 GCM155R71C104KA55D Murata
Bandgap Supply 1 0.047 µF, 50 V, ± 10%, X7R, AEC-Q200 Grade 1, 0402 CGA2B3X7R1H473K050BB TDK
VPP Supply 1 0.1 µF, 16 V, ± 10%, X7R, 0402 GCM155R71C104KA55D Murata
GUID-A0F7FC5A-6736-42DC-B085-DB912D283418-low.png Figure 2-4 AM273x GPEVM Excerpt – 1.2 V Power Decoupling Schematic
GUID-8D381868-CCA0-4A72-9298-17B36860F6BA-low.png Figure 2-5 AM273x GPEVM Excerpt – 1.8 V Digital I/O Decoupling Schematic
GUID-B1D1347A-2BDE-469D-8848-CB37C90D682A-low.png Figure 2-6 AM273x GPEVM Excerpt – 3.3 V Digital I/O Decoupling Schemati
GUID-E83F1424-E1B0-445A-9FC7-6F006E889A84-low.png Figure 2-7 AM273x GPEVM Excerpt – SRAM Decoupling Schematic
GUID-FA314CC5-91B2-4711-BD87-1AD989EF62D5-low.png Figure 2-8 AM273x GPEVM Excerpt – Additional Decoupling Schematic