SPRAD62 February   2023 F29H850TU , F29H859TU-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Serial Port Design Methodology
    1. 2.1 Step 1: Understand Design Requirements
    2. 2.2 Step 2: Identify Required Inputs to the CLB Tile
      1. 2.2.1 GPIO Input Qualification
      2. 2.2.2 CLB Input Settings
    3. 2.3 Step 3: Identify Required Outputs from CLB Logic
      1. 2.3.1 Synchronizing Outputs Signals
      2. 2.3.2 Output Signal Conditioning
    4. 2.4 Step 4: Design the CLB Logic
      1. 2.4.1 Resource Allocation
      2. 2.4.2 Exchanging Data Between CLB FIFOs and MCU RAM
      3. 2.4.3 CLB Logic Status and Trigger Flags
        1. 2.4.3.1 Status/Flag Bits
        2. 2.4.3.2 Trigger Bits
    5. 2.5 Step 5: Simulate the Logic Design
    6. 2.6 Step 6: Test the CLB Logic
  5. 3Example A: Using the CLB to Input and Output a TDM Stream in Audio Applications
    1. 3.1 Example Overview
    2. 3.2 Step 1: Understand Design Requirements
    3. 3.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 3.4 Step 3: Identify Required Outputs from CLB Logic
    5. 3.5 Step 4: Design the CLB Logic
      1. 3.5.1 Resource Allocation
      2. 3.5.2 TDM Word Counter
      3. 3.5.3 FSYNC and DATA1 Output Synchronization
    6. 3.6 Step 5: Simulate the Logic Design
    7. 3.7 Step 6: Test the CLB Logic
      1. 3.7.1 Hardware Setup and Connections
      2. 3.7.2 Software Setup
      3. 3.7.3 Testing Output Setup and Hold Times
      4. 3.7.4 Testing Data Integrity
  6. 4Example B: Using the CLB to Implement a Custom Communication Bus for LED Driver in Lighting Applications
    1. 4.1 Example Overview
    2. 4.2 Step 1: Understand Design Requirements
    3. 4.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 4.4 Step 3: Identify Required Outputs From CLB Logic
    5. 4.5 Step 4: Design the CLB Logic
      1. 4.5.1 TX Tile Logic
      2. 4.5.2 RX Tile Logic
      3. 4.5.3 Data Clocking
    6. 4.6 Step 5: Simulate the Logic Design
    7. 4.7 Step 6: Test the CLB Logic
      1. 4.7.1 Hardware Setup and Connections
      2. 4.7.2 Software Setup
      3. 4.7.3 Testing Output Setup and Hold Times
  7. 5References

3.6 Step 5: Simulate the Logic Design

A data receive operation is simulated in Figure 3-9. For this simulation a simple pattern of 0xAAAA AAAA is used as data input. The simulation shows the transition between the last bit of the last word in the TDM frame and the start of a new frame.

GUID-20220916-SS0I-K51D-S4HG-K5J3TTGDKPSR-low.png Figure 3-9 TDM-8 Data Receive Simulation

A data transmit operation is simulated in Figure 3-10. The simulation shows the transition between the last bit of the last word in the TDM frame and the start of a new frame. For this simulation a pattern of 0x5555 5554 is continuously transmitted to highlight the potential for a brief glitch at the output of the serializer in between serial words. Since the serializer must be loaded after it has shifted its counter value to avoid losing the most significant bit in the transmit word, there is a brief period of time when the serializer output is invalid.

GUID-20220916-SS0I-D6DW-5XVN-NDHX9GXRQR9G-low.png Figure 3-10 TDM-8 Data Transmit Simulation

Notice that in this TDM example the HLC has been configured to push the value in C0 to the FIFO and then load a new value to C1 (see Figure 3-5). This is done deliberately to ensure C1 is loaded after the rising edge of BCLK_IN. Since the HLC action is triggered on the falling edge of BCLK and the serializer action is dependent on the rising edge of BCLK, there is an inherent dependency on the BCLK_IN period. If the BCLK_IN period is extended (BCLK_IN frequency is reduced or CLB clock frequency is increased), there is a risk that the C1 update happens before the rising edge of the clock, which causes a loss of the most-significant bit in the serial word.

As seen in Figure 3-10, there is a delay between the output data and the input FSYNC and BCLK. In order to output a FSYNC and DATA1 signal that are synchronized with each other, two FSMs are used to latch and delay these two signals. The simulation result of this feature is shown in Figure 3-11.

GUID-20221017-SS0I-8TKQ-WDS8-HVJTLR1HRQBD-low.png Figure 3-11 FSYNC and DATA1 Synchronization