SPRAD62 February   2023 F29H850TU , F29H859TU-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Serial Port Design Methodology
    1. 2.1 Step 1: Understand Design Requirements
    2. 2.2 Step 2: Identify Required Inputs to the CLB Tile
      1. 2.2.1 GPIO Input Qualification
      2. 2.2.2 CLB Input Settings
    3. 2.3 Step 3: Identify Required Outputs from CLB Logic
      1. 2.3.1 Synchronizing Outputs Signals
      2. 2.3.2 Output Signal Conditioning
    4. 2.4 Step 4: Design the CLB Logic
      1. 2.4.1 Resource Allocation
      2. 2.4.2 Exchanging Data Between CLB FIFOs and MCU RAM
      3. 2.4.3 CLB Logic Status and Trigger Flags
        1. 2.4.3.1 Status/Flag Bits
        2. 2.4.3.2 Trigger Bits
    5. 2.5 Step 5: Simulate the Logic Design
    6. 2.6 Step 6: Test the CLB Logic
  5. 3Example A: Using the CLB to Input and Output a TDM Stream in Audio Applications
    1. 3.1 Example Overview
    2. 3.2 Step 1: Understand Design Requirements
    3. 3.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 3.4 Step 3: Identify Required Outputs from CLB Logic
    5. 3.5 Step 4: Design the CLB Logic
      1. 3.5.1 Resource Allocation
      2. 3.5.2 TDM Word Counter
      3. 3.5.3 FSYNC and DATA1 Output Synchronization
    6. 3.6 Step 5: Simulate the Logic Design
    7. 3.7 Step 6: Test the CLB Logic
      1. 3.7.1 Hardware Setup and Connections
      2. 3.7.2 Software Setup
      3. 3.7.3 Testing Output Setup and Hold Times
      4. 3.7.4 Testing Data Integrity
  6. 4Example B: Using the CLB to Implement a Custom Communication Bus for LED Driver in Lighting Applications
    1. 4.1 Example Overview
    2. 4.2 Step 1: Understand Design Requirements
    3. 4.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 4.4 Step 3: Identify Required Outputs From CLB Logic
    5. 4.5 Step 4: Design the CLB Logic
      1. 4.5.1 TX Tile Logic
      2. 4.5.2 RX Tile Logic
      3. 4.5.3 Data Clocking
    6. 4.6 Step 5: Simulate the Logic Design
    7. 4.7 Step 6: Test the CLB Logic
      1. 4.7.1 Hardware Setup and Connections
      2. 4.7.2 Software Setup
      3. 4.7.3 Testing Output Setup and Hold Times
  7. 5References

2.2 Step 2: Identify Required Inputs to the CLB Tile

In most cases, input signals need to be passed to the CLB tile. Generally, there are three categories of signals to consider:

  • External serial bus signals sampled through GPIO pins. These include, for example, serial bus clock, frame, and data signals.
  • On-chip peripheral signals used in the operation of the CLB logic. For example, a clock signal generated using a PWMnA pin or a timer interrupt.
  • GPREG bits directly controlled by the CPU. These GPREG bits can be used to trigger an action in the CLB tile or enable/disable a specific feature.

These input signals can be connected to the eight CLB tile inputs using the CLB global and local muxes in combination with the different XBARs on the device. For more information, see the device-specific TRM.

There are often multiple paths which can be used to connect a CLB tile to an input signal. Table 2-1 lists the recommended path to bring in these signals to the CLB tile boundary.

Table 2-1 Recommended Paths for Input Signals
Input Signal TypeRecommended Input Path
External serial bus signals (for example, serial bus clock, frame, and data signals)GPIO pin ⇨ CLB input XBAR 1 ⇨ CLB local mux ⇨ CLB input
Internal on-chip peripheral signals (for example, clock signal generated using a PWMnA)Peripheral signal ⇨ CLB global mux or CLB local mux ⇨ CLB input
Custom signal directly controlled by CPUMemory-mapped GPREG bit ⇨ CLB input
  1. CLB input XBAR is not available on all C2000 real-time microcontrollers. On those devices, external signals can be brought to the tile boundary using the GPIO XBAR and CLB XBAR. For more information, see the device-specific TRM.