SPRAD62 February   2023 F29H850TU , F29H859TU-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Serial Port Design Methodology
    1. 2.1 Step 1: Understand Design Requirements
    2. 2.2 Step 2: Identify Required Inputs to the CLB Tile
      1. 2.2.1 GPIO Input Qualification
      2. 2.2.2 CLB Input Settings
    3. 2.3 Step 3: Identify Required Outputs from CLB Logic
      1. 2.3.1 Synchronizing Outputs Signals
      2. 2.3.2 Output Signal Conditioning
    4. 2.4 Step 4: Design the CLB Logic
      1. 2.4.1 Resource Allocation
      2. 2.4.2 Exchanging Data Between CLB FIFOs and MCU RAM
      3. 2.4.3 CLB Logic Status and Trigger Flags
        1. 2.4.3.1 Status/Flag Bits
        2. 2.4.3.2 Trigger Bits
    5. 2.5 Step 5: Simulate the Logic Design
    6. 2.6 Step 6: Test the CLB Logic
  5. 3Example A: Using the CLB to Input and Output a TDM Stream in Audio Applications
    1. 3.1 Example Overview
    2. 3.2 Step 1: Understand Design Requirements
    3. 3.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 3.4 Step 3: Identify Required Outputs from CLB Logic
    5. 3.5 Step 4: Design the CLB Logic
      1. 3.5.1 Resource Allocation
      2. 3.5.2 TDM Word Counter
      3. 3.5.3 FSYNC and DATA1 Output Synchronization
    6. 3.6 Step 5: Simulate the Logic Design
    7. 3.7 Step 6: Test the CLB Logic
      1. 3.7.1 Hardware Setup and Connections
      2. 3.7.2 Software Setup
      3. 3.7.3 Testing Output Setup and Hold Times
      4. 3.7.4 Testing Data Integrity
  6. 4Example B: Using the CLB to Implement a Custom Communication Bus for LED Driver in Lighting Applications
    1. 4.1 Example Overview
    2. 4.2 Step 1: Understand Design Requirements
    3. 4.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 4.4 Step 3: Identify Required Outputs From CLB Logic
    5. 4.5 Step 4: Design the CLB Logic
      1. 4.5.1 TX Tile Logic
      2. 4.5.2 RX Tile Logic
      3. 4.5.3 Data Clocking
    6. 4.6 Step 5: Simulate the Logic Design
    7. 4.7 Step 6: Test the CLB Logic
      1. 4.7.1 Hardware Setup and Connections
      2. 4.7.2 Software Setup
      3. 4.7.3 Testing Output Setup and Hold Times
  7. 5References

4.6 Step 5: Simulate the Logic Design

A data receive operation is simulated in Figure 4-15. For this simulation a simple pattern of 0xAAAA is used as data input. The simulation shows the beginning of the frame indicated by the START bit, the capture of the full received word, and the verification of the CHECK bit.

GUID-20220916-SS0I-MQCL-CQHW-BJMPHTMLCJZC-low.png Figure 4-15 Data Receive Simulation for LED Driver

A second data receive simulation is shown in Figure 4-16. In this simulation, an incorrect CHECK bit is added to the incoming data stream to verify the operation of the CHECK bit logic. The simulation shows the output of the LUT1 block go high to indicate a CHECK bit error is detected.

GUID-20220916-SS0I-MTKX-0Z0M-6J0BKJ3DLQRK-low.png Figure 4-16 Check Bit Error Logic Simulation

Finally, the simulation in Figure 4-17 shows the detection of the END bits. The FSM0 block transitions the CLB logic to the IDLE state upon detection of the END bits.

GUID-20220916-SS0I-R9XN-WCW5-TPVHZG5TZJK4-low.png Figure 4-17 END Frame Detection
Note: Both a receive interrupt and CHECK bit error (not shown) will be generated during the END bits. The CPU code will have to always discard the last word in a frame as this corresponds to the END bits.

A data transmit operation is simulated in Figure 4-18. The simulation shows the transmission of a single 0x5555 word, starting from the START bit and ending with the END frame. To simplify the CLB logic, the START bit is implemented by allowing the tile to transmit a 0xFFFF word. The START bit is generated on the 17th clock cycle using the CHECK bit logic of the tile. Similarly, to generate the END frame, the CLB logic simply sets the CLB_SOUT signal to 1 at the end of the last word transmission. The CLB logic depends on the CPU to wait at least 18 PWM_SCLKX2 cycles before starting a new data transmission.

GUID-20220916-SS0I-W09Q-3WLB-WTSCTRPQNXNS-low.png Figure 4-18 Data Transmit Simulation for LED Driver

An output glitch is observed during data transmit operations due to the delay in updating the output serializer (Counter 1). Figure 4-19 shows the internal delays starting from the PWM_SCLKX2 low edge to the final update of the output serializer. The result of the glitch is a reduced setup time for the receiving device. The setup time should not be calculated from the rising edge of the PWM_SCLKX2 signal since this clock will also be delayed as it passes through the CLB tile. Instead, the setup time should be calculated from the CLB_SCLKX2 signal. This signal is a delayed version of PWM_SCLKX2 which the receiving device will observe.

GUID-20220916-SS0I-VGDP-ZBG6-WLWM8V8KB80C-low.png Figure 4-19 Output Glitch

The glitch can be elimited by latching the serializer output before passing to CLB_SOUT. However, this approach is not used since at least two CLB cycles of setup time are expected per the transmit simulation which is enough to meet the 10ns setup time required by the LP5891-Q1 device.