In all likelihood, the output signals generated by the CLB is generated by different logic blocks in the CLB tile. This can lead to different delay paths in each output signal. In order to maximize the setup and hold times seen by the receiving device, the different CLB outputs can be synchronized to each other using a bus clock and simple flip-flops, see Figure 2-1. The flip-flops can be implemented using finite state machine (FSM) blocks in the CLB tile. However, due to limited CLB tile resources, it is best to use this option only when absolutely needed.

As an example of the need for synchronization logic, consider the simulation in Figure 2-2, which shows two inputs, in1 and in2, changing state at slightly different times. These two signals are synchronized to each other using a third “clock” signal, in0 using two edge-triggered D-type flip-flops implemented using the two FSMs. As can be seen from the simulation, each FSM latches and delays its input signal using the “clock” signal in0. As a result, both FSM outputs are synchronized with each other.

The logic equations for each FSM output and state variable are shown in Figure 2-3. Notice that both FSM out and s0 are set to the same equation and either signal can be used to drive the final output. There is a 1-cycle delay between both signals due to out being a purely combinatorial output, while s0 is always updated on the next CLB clock cycle. Also note that in this simulation, in0 input filter is setup for synchronous, rising-edge detect.