SPRAD66A February   2023  – December 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Ax/AM62Px LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK0 and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
    16. 2.16 Data Bus Inversion
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 System Level Simulation
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Eye Quality
        2. 3.5.3.2 Delay Report
        3. 3.5.3.3 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Appendix: SOC Package Delays
  8. 5References
  9. 6Revision History

3.1 Board Model Extraction

Note: This section contains various information from J7 devices and board designs. The specific details only apply to J7 board designs, but are provided here as an examples for AM62Ax/AM62Px board designs.

The board level extraction guidelines listed below are intended to work in any EDA extraction tool and are not tool-specific. It is important to follow the steps outlined in Section 3.2 through Section 3.4 immediately after completing touchstone model extractions. The design should be checked with these steps prior to running IBIS simulations.

  1. For DDR extractions, extract power (VDDS_DDR/VDDQ) and signal nets together in a 3D-EM solver.
  2. Use wide-band models. It is recommended to extract from DC to at least until 6x the Nyquist frequency (for example, for LPDDR4-3733 extract the model at least until 11.2 GHz).
  3. Check the board stack-up for accurate layer thickness and material properties.
    1. It is recommended to use Djordjevic-Sarkar models for the dielectric material definition.
  4. Use accurate etch profiles and surface roughness for the signal traces across all layers in the stack-up.
  5. If the board layout is cut prior to extraction (to reduce simulation time), define a cut boundary that is at least 0.25 inch away from the signal and power nets.
  6. Check the via padstack definitions.
    1. Ensure that the non-functional internal layer pads on signal vias are modeled the same way they would be fabricated.
    2. These non-functional internal layer pads on signal vias are not recommended by TI.
  7. Use Spice/S-parameter models (typically available from the vendor) for modeling all passives in the system.
  8. Obtain SoC package model for AM62Ax/AM62Px from your TI representative.