The CK and ADDR_CTRL net classes are routed similarly, and are skew matched from the DDR controller in the processor to the LPDDR4 SDRAM to ensure that the ADDR_CTRL signals are properly sampled at the SDRAM. The CK0 net class requires more care because it runs at a higher transition rate and are differential. The CK and ADDR_CTRL topology is balanced ‘T’.

Figure 2-6 shows the topology of the CK0 net class. Figure 2-7 and Figure 2-8 shows the topologies for the corresponding ADDR_CTRL_A net class. Note some of the signals within the group are shared between the memory channels, while other signals are dedicated for each channel. Skew matching requirements for the routing segments are detailed in Table 2-6.

Figure 2-6 LPDDR4 CK Topology

Figure 2-7 LPDDR4 ADDR_CTRL Topology/Branched Signals

Figure 2-8 LPDDR4 ADDR_CTRL Topology/Point-to-Point Signals

It is recommended to minimize layer transitions during routing. If a layer transition is necessary, it is preferable to transition to a layer using the same reference plane. If this cannot be accommodated, ensure there are nearby stitching vias to allow the return currents to transition between reference planes. The goal is to minimize the size of the return current path thus minimizing the inductance in this path. Lack of these stitching vias results in impedance discontinuities in the signal path that increase crosstalk and signal distortion.

There are no stubs or termination allowed on the nets of the CK and ADDR_CTRL group topologies. All test and probe access points must be in line without any branches or stubs.