SPRAD66A February   2023  – December 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Ax/AM62Px LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK0 and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
    16. 2.16 Data Bus Inversion
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 System Level Simulation
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Eye Quality
        2. 3.5.3.2 Delay Report
        3. 3.5.3.3 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Appendix: SOC Package Delays
  8. 5References
  9. 6Revision History

3.4 Time Domain Reflectometry (TDR) Analysis

As a lot of the design fixes are targeted towards maintaining uniform trace impedance, an important analysis method used in assessing the quality of the design is the Time Domain Reflectometry (TDR) analysis. This plots the impedance of a trace as a function of its length, as shown in Figure 3-1.

GUID-1BD87F34-67E7-4548-8725-C6C4448396CA-low.pngFigure 3-1 TDR Plot Example With Impedance Mismatch

As shown in Figure 3-1, the TDR plot highlights impedance discontinuities in the trace from one end to the other. This method depends on a reflected waveform from the far-end of the trace. The delay in the plot corresponding to a particular point in the trace actually corresponds to 2 times the distance of that point from the source, owing to the round trip time. This needs to be factored in for assessing the source of impedance discontinuities.

The TDR plot can be generated by reading in the S-parameter models generated by the extraction tool and assessing them in “Time-Domain” mode. A standard EDA simulator such as HyperLynx can perform this function. It is recommended to optimize the design to within a ± 5% deviation from the nominal trace impedance.

The TDR plots are not pass/fail tests, but rather is more of a guide to check if the design has a reasonable chance of performing a the required level.