SPRAD66B February 2023 – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1 , AM62P , AM62P-Q1
The data line topology is always point-to-point for LPDDR4 implementations, and is broken up into four different byte lanes. TI recommends to minimize layer transitions during routing. If a layer transition is necessary, then this is better to transition to a layer using the same reference plane. If this cannot be accommodated, then make sure there are nearby ground vias to allow the return currents to transition between reference planes. The goal is to provide a low inductance path for the return current. To optimize the skew matching, TI recommends routing all nets within a single data routing group on one layer where all nets have the exact same number of vias and the same via barrel length.
DQSP and DQSN lines are point-to-point signals routed as a differential pair. Figure 2-9 illustrates the DQSP and DQSN connection topology.
DQ and DM lines are point-to-point signals routed as single-ended. Figure 2-10 illustrates the DQ and DM connection topology.
There are no stubs or termination allowed on the nets of the data group topologies. All test and probe access points must be in line without any branches or stubs.