SPRAD66B February   2023  – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK0 and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
    16. 2.16 Data Bus Inversion
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 System Level Simulation
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Eye Quality
        2. 3.5.3.2 Delay Report
        3. 3.5.3.3 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Additional Information: SOC Package Delays
  8. 5Summary
  9. 6References
  10. 7Revision History

2.3 LPDDR4 Interface Schematics

The LPDDR4 interface schematics vary, depending upon the number of ranks implemented. General connectivity is straightforward and consistent between the implementations. Figure 2-1 illustrates a 32-bit, single-rank LPDDR4 implementation. If dual rank is required, then the additional chip select is included. Figure 2-2 illustrates a 32-bit, dual-rank LPDDR4 implementation. On select devices, 16-bit single-rank LPDDR4 implementation are support, see Figure 2-3.

Note: Though LPDDR4 SDRAMs pin out two separate channels, independent channel use is not supported by this processor.
32-Bit, Single-Rank LPDDR4 Implementation Figure 2-1 32-Bit, Single-Rank LPDDR4 Implementation
  1. When used with LPDDR4, the DDR0_CAS_n and DDR0_RAS_n pins output copies of the chip selects to support point to point connections to Channel B chip selects on the LPDDR4 device. DDR0_CAS_n = copy of CS1 for LPDDR4_CS1_B, DDR0_RAS_n = copy of CS0 for LPDDR4_CS0_B.
  2. An external 240Ω ±1% resistor must be connected between this pin and VSS. The maximum power dissipation for the resistor is 5.2mW. No external voltage must be applied to this pin. Tolerance of ±1% required throughout life of component or product.
  3. RESET_n shall have an external 10k pull-down resistor to control RESET low until the DDR controller drives the signal. RESET_n has no length matching requirement.
32-Bit, Dual Rank LPDDR4 Implementation Figure 2-2 32-Bit, Dual Rank LPDDR4 Implementation
  1. When used with LPDDR4, the DDR0_CAS_n and DDR0_RAS_n pins output copies of the chip selects to support point to point connections to Channel B chip selects on the LPDDR4 device. DDR0_CAS_n = copy of CS1 for LPDDR4_CS1_B, DDR0_RAS_n = copy of CS0 for LPDDR4_CS0_B.
  2. An external 240Ω ±1% resistor must be connected between this pin and VSS. The maximum power dissipation for the resistor is 5.2mW. No external voltage must be applied to this pin. Tolerance of ±1% required throughout life of component or product.
  3. RESET_n shall have an external 10k pull-down resistor to control RESET low until the DDR controller drives the signal. RESET_n has no length matching requirement.
16-Bit, Single Rank LPDDR4 Implementation Figure 2-3 16-Bit, Single Rank LPDDR4 Implementation
  1. When used with LPDDR4, the DDR0_CAS_n and DDR0_RAS_n pins output copies of the chip selects to support point to point connections to Channel B chip selects on the LPDDR4 device. DDR0_CAS_n = copy of CS1 for LPDDR4_CS1_B, DDR0_RAS_n = copy of CS0 for LPDDR4_CS0_B.
  2. An external 240Ω ±1% resistor must be connected between this pin and VSS. The maximum power dissipation for the resistor is 5.2mW. No external voltage must be applied to this pin. Tolerance of ±1% required throughout life of component or product.
  3. RESET_n shall have an external 10k pull-down resistor to control RESET low until the DDR controller drives the signal. RESET_n has no length matching requirement.