SPRAD85B
September 2024 – December 2024
AM62A3
,
AM62A3-Q1
,
AM62A7
,
AM62A7-Q1
,
AM62D-Q1
1
Abstract
Trademarks
1
Introduction
1.1
Before Getting Started With the Custom Board Design
1.2
Processor Selection
1.3
Technical Documentation
1.3.1
Updated SK Schematics With Design, Review and Cad Notes Added
1.3.1.1
AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
1.3.1.2
AM62D-Q1
1.3.2
FAQs to Support Custom Board Design
1.4
Custom Board Design Documentation
2
Block Diagram
2.1
Constructing the Block Diagram
2.2
Configuring the Boot Mode
2.3
Confirming PinMux (PinMux Configuration)
3
Power Supply
3.1
Power Supply Architecture
3.1.1
Integrated Power
3.1.2
Discrete Power
3.2
Power (Supply) Rails
3.2.1
Core Supply
3.2.2
Peripheral Power Supply
3.2.3
Dynamic Switching Dual-Voltage IO Supply LDO
3.2.4
Internal LDOs for IO Groups (Processor)
3.2.5
Dual-Voltage IOs (for Processor IO Groups)
3.2.6
VPP (eFuse ROM programming) Supply
3.3
Determining Board Power Requirements
3.4
Power Supply Filters
3.5
Power Supply Decoupling and Bulk Capacitors
3.5.1
Note on PDN Target Impedance
3.6
Power Supply Sequencing
3.7
Supply Diagnostics
3.8
Power Supply Monitoring
4
Processor Clocking
4.1
Processor External Clock Source
4.1.1
Unused WKUP_LFOSC0
4.1.2
LVCMOS Digital Clock Source
4.1.3
Crystal Selection
4.2
Processor Clock Outputs
5
JTAG (Joint Test Action Group)
5.1
JTAG / Emulation
5.1.1
Configuration of JTAG / Emulation
5.1.1.1
BSDL File
5.1.2
Implementation of JTAG / Emulation
5.1.3
Connection of JTAG Interface Signals
6
Configuration (Processor) and Initialization (Processor and Device)
6.1
Processor Reset
6.2
Latching of Boot Mode Configuration
6.3
Resetting the Attached Devices
6.4
Watchdog Timer
7
Processor Peripherals
7.1
Selecting Peripherals Across Domains
7.2
Memory Controller (DDRSS)
7.2.1
Processor DDR Subsystem and Device Register Configuration
7.2.2
Calibration Resistor Connection for DDRSS
7.2.3
Attached Memory Device ZQ and Reset_N Connection
7.3
Media and Data Storage Interfaces
7.4
Common Platform Ethernet Switch 3-port Gigabit (CPSW3G - for Ethernet Interface)
7.5
Programmable Real-Time Unit Subsystem (PRUSS)
7.6
Universal Serial Bus (USB) Subsystem
7.7
General Connectivity Peripherals
7.8
Display Subsystem (DSS)
7.8.1
AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
7.8.2
AM62D-Q1
7.9
Camera Interface
7.10
Connection of Processor Power Supply Pins, Unused Peripherals and IOs
7.10.1
External Interrupt (EXTINTn)
7.10.2
RSVD Reserved Pins (Signals)
8
Interfacing of Processor IOs (LVCMOS or Open-Drain or Fail-Safe Type IO Buffers) and Simulations
8.1
IBIS Model
8.2
IBIS-AMI Model
9
Processor Current Rating and Thermal Analysis
9.1
Power Estimation
9.2
Maximum Current Rating for Different Supply Rails
9.3
Power Modes
9.4
Thermal Design Guidelines
9.4.1
Thermal Model
9.4.2
VTM (Voltage Thermal Management Module)
10
Schematics:- Design, Capture, Entry and Review
10.1
Selection of Components and Values
10.2
Schematic Design and Capture
10.3
Schematics Review
11
Floor Planning, Layout, Routing Guidelines, Board Layers and Simulation
11.1
Escape Routing for PCB Design
11.2
LPDDR4 Design and Layout Guidelines
11.3
High-Speed Differential Signals Routing Guidelines
11.4
Board Layer Count and Stack-up
11.4.1
Simulation Recommendations
11.5
Reference for Steps to be Followed for Running Simulation
12
Custom Board Assembly and Testing
12.1
Guidelines and Board Bring-up Tips
13
Device Handling and Assembly
13.1
Soldering Recommendations
13.1.1
Additional References
14
References
14.1
AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
14.2
AM62D-Q1
14.3
Common
15
Terminology
16
Revision History
15
Terminology
BSDL
Boundary-Scan Description Language
CAN
Controller Area Network
CAN-FD
Controller Area Network Flexible Data-Rate
CPPI
Communications Port Programming Interface
CPSW3G
Common Platform Ethernet Switch 3-port Gigabit
CSIRX
Camera Streaming Interface Receiver
DPI
Display Parallel Interface
DRD
Dual-Role Device
DSI
Display Serial Interface
DSITX
Display Serial Interface transmitter
E2E
Engineer to Engineer
ECAP
Enhanced Capture
ECC
Error-Correcting Code
eMMC
embedded Multi-Media Card
EMU
Emulation Control
EPWM
Enhanced Pulse-Width Modulator
EQEP
Enhanced Quadrature Encoder Pulse
FAQ
Frequently Asked Question
GEMAC
Gigabit Ethernet Media Access Controller
GPIO
General Purpose Input/Output
GPMC
General-Purpose Memory Controller
HS-RTDX
High-Speed Real Time Data eXchange
I2C
Inter-Integrated Circuit
IBIS
Input/Output Buffer Information Specification
JTAG
Joint Test Action Group
LDO
Low-Dropout
LVCMOS
Low Voltage Complementary Metal Oxide Semiconductor
LVDS
Low Voltage Differential Signaling
MAC
Media Access Controller
MCASP
Multichannel Audio Serial Ports
MCSPI
Multichannel Serial Peripheral Interfaces
MCU
Micro Controller Unit
MMC
Multi-Media Card
MSL
Moisture Sensitivity Level
OPP
Operating Performance Point
OSPI
Octal Serial Peripheral Interface
OTP
One-Time Programmable
PCB
Printed Circuit Board
PMIC
Power Management Integrated Circuit
POR
Power-on Reset
QSPI
Quad Serial Peripheral Interface
RGMII
Reduced Gigabit Media Independent Interface
RMII
Reduced Media Independent Interface
SD
Secure Digital
SDIO
Secure Digital Input Output
SDK
Software Development Kit
SPI
Serial Peripheral Interface
TCK
Test Clock Input
TDI
Test Data Input
TDO
Test Data Output
TMS
Test Mode Select Input
TRM
Technical Reference Manual
TRSTn
Test Reset
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
VCA
Via Channel Array
VTM
Voltage Thermal Management Module
WKUP
Wakeup
XDS
eXtended Development System