SPRAD85B September   2024  – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Before Getting Started With the Custom Board Design
    2. 1.2 Processor Selection
    3. 1.3 Technical Documentation
      1. 1.3.1 Updated SK Schematics With Design, Review and Cad Notes Added
        1. 1.3.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
        2. 1.3.1.2 AM62D-Q1
      2. 1.3.2 FAQs to Support Custom Board Design
    4. 1.4 Custom Board Design Documentation
  5. 2 Block Diagram
    1. 2.1 Constructing the Block Diagram
    2. 2.2 Configuring the Boot Mode
    3. 2.3 Confirming PinMux (PinMux Configuration)
  6. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power
      2. 3.1.2 Discrete Power
    2. 3.2 Power (Supply) Rails
      1. 3.2.1 Core Supply
      2. 3.2.2 Peripheral Power Supply
      3. 3.2.3 Dynamic Switching Dual-Voltage IO Supply LDO
      4. 3.2.4 Internal LDOs for IO Groups (Processor)
      5. 3.2.5 Dual-Voltage IOs (for Processor IO Groups)
      6. 3.2.6 VPP (eFuse ROM programming) Supply
    3. 3.3 Determining Board Power Requirements
    4. 3.4 Power Supply Filters
    5. 3.5 Power Supply Decoupling and Bulk Capacitors
      1. 3.5.1 Note on PDN Target Impedance
    6. 3.6 Power Supply Sequencing
    7. 3.7 Supply Diagnostics
    8. 3.8 Power Supply Monitoring
  7. 4 Processor Clocking
    1. 4.1 Processor External Clock Source
      1. 4.1.1 Unused WKUP_LFOSC0
      2. 4.1.2 LVCMOS Digital Clock Source
      3. 4.1.3 Crystal Selection
    2. 4.2 Processor Clock Outputs
  8. 5 JTAG (Joint Test Action Group)
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
        1. 5.1.1.1 BSDL File
      2. 5.1.2 Implementation of JTAG / Emulation
      3. 5.1.3 Connection of JTAG Interface Signals
  9. 6 Configuration (Processor) and Initialization (Processor and Device)
    1. 6.1 Processor Reset
    2. 6.2 Latching of Boot Mode Configuration
    3. 6.3 Resetting the Attached Devices
    4. 6.4 Watchdog Timer
  10. 7 Processor Peripherals
    1. 7.1  Selecting Peripherals Across Domains
    2. 7.2  Memory Controller (DDRSS)
      1. 7.2.1 Processor DDR Subsystem and Device Register Configuration
      2. 7.2.2 Calibration Resistor Connection for DDRSS
      3. 7.2.3 Attached Memory Device ZQ and Reset_N Connection
    3. 7.3  Media and Data Storage Interfaces
    4. 7.4  Common Platform Ethernet Switch 3-port Gigabit (CPSW3G - for Ethernet Interface)
    5. 7.5  Programmable Real-Time Unit Subsystem (PRUSS)
    6. 7.6  Universal Serial Bus (USB) Subsystem
    7. 7.7  General Connectivity Peripherals
    8. 7.8  Display Subsystem (DSS)
      1. 7.8.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
      2. 7.8.2 AM62D-Q1
    9. 7.9  Camera Interface
    10. 7.10 Connection of Processor Power Supply Pins, Unused Peripherals and IOs
      1. 7.10.1 External Interrupt (EXTINTn)
      2. 7.10.2 RSVD Reserved Pins (Signals)
  11. 8 Interfacing of Processor IOs (LVCMOS or Open-Drain or Fail-Safe Type IO Buffers) and Simulations
    1. 8.1 IBIS Model
    2. 8.2 IBIS-AMI Model
  12. 9 Processor Current Rating and Thermal Analysis
    1. 9.1 Power Estimation
    2. 9.2 Maximum Current Rating for Different Supply Rails
    3. 9.3 Power Modes
    4. 9.4 Thermal Design Guidelines
      1. 9.4.1 Thermal Model
      2. 9.4.2 VTM (Voltage Thermal Management Module)
  13. 10Schematics:- Design, Capture, Entry and Review
    1. 10.1 Selection of Components and Values
    2. 10.2 Schematic Design and Capture
    3. 10.3 Schematics Review
  14. 11Floor Planning, Layout, Routing Guidelines, Board Layers and Simulation
    1. 11.1 Escape Routing for PCB Design
    2. 11.2 LPDDR4 Design and Layout Guidelines
    3. 11.3 High-Speed Differential Signals Routing Guidelines
    4. 11.4 Board Layer Count and Stack-up
      1. 11.4.1 Simulation Recommendations
    5. 11.5 Reference for Steps to be Followed for Running Simulation
  15. 12Custom Board Assembly and Testing
    1. 12.1 Guidelines and Board Bring-up Tips
  16. 13Device Handling and Assembly
    1. 13.1 Soldering Recommendations
      1. 13.1.1 Additional References
  17. 14References
    1. 14.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
    2. 14.2 AM62D-Q1
    3. 14.3 Common
  18. 15Terminology
  19. 16Revision History

7.9 Camera Interface

The processor family supports one Camera Serial interface (CSI-2) Receiver with 4 Lane D-PHY. Support for 1, 2, 3 or 4 data lane mode. Refer Multimedia, Camera Serial interface (CSI-2) Receiver with Lane D-PHY section in the Features chapter of device-specific data sheet for supported data rate.

The DPHY-RX supports a single clock lane and all the data lanes are clocked at the same frequency. The frame rate is determined by start-of-frame, end-of-frame signaling and allows handling the input sources with different frame rates per channel.

Refer Pin Connectivity Requirements section of the device-specific data sheet for connecting interface pins and supply pins when CSIRX0 interface is not used.

For more details, refer the Camera Serial Interface Receiver (CSI_RX_IF) and MIPI D-PHY Receiver (DPHY_RX) sections in the Peripherals chapter of the device-specific TRM.

For more information on CSIRX0, see the [FAQ] AM625 / AM623 / AM625SIP / AM625-Q1 / AM62A / AM62P Custom board hardware design – CSI-2 capabilities. The FAQ is generic and can also be used for AM62D-Q1 processor family.