SPRAD90 February   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Change Cortex-A53 Clock Frequency
  4. 2Processor Core Benchmarks
    1. 2.1 Dhrystone
  5. 3Compute and Memory System Benchmarks
    1. 3.1 Memory Bandwidth and Latency
      1. 3.1.1 LMBench
      2. 3.1.2 STREAM
      3. 3.1.3 Critical Memory Access Latency
    2. 3.2 CoreMark-Pro
    3. 3.3 Fast Fourier Transform
    4. 3.4 Cryptographic Benchmarks
  6. 4Application Benchmarks
    1. 4.1 Machine Learning Inference
  7. 5References

3.1.3 Critical Memory Access Latency

This section provides read memory access latency measurements from processors in AM62Ax to various memory destinations in the system. The measurements where made on the AM62Ax platform using bare-metal silicon verification tests that are not currently included in the SDK. The tests executed on A53, C7x and R5F processor out of the LPDDR4. Each test includes a loop of 8192 iterations to read a total of 32 KiB of data. The number of cycles for each test were counted and divided by the respective processor clock frequency to obtain latency time. #GUID-0541ED62-8716-4568-BB03-BEE6D8B7436A/GUID-92F69D7E-5B50-4B49-8FA9-E62257F7DE7A shows the average latency results.

Table 3-4 Critical Memory Access Latency of A53, C7x, R5F MCU, and R5F WKUP
Memory Arm-Cortex-A53
(Avg ns)		 C7x DSP (Avg ns) Arm-Cortex-R5F MCU (Avg ns) Arm-Cortex-R5F WKUP (Avg ns)
LPDDR4 137 154 202 172
OCSRAM MAIN 59 57 122 77
OCSRAM MCU 120 118 58 85
OCSRAM WKUP 210 189 203 156
C7X SRAM - Local Path NA 20 NA NA
C7X SRAM - External Path 80 NA 151 103
R5F MCU TCM - Local Path NA NA 1 NA
R5F MCU TCM - External Path 143 144 NA 120
R5F WKUP TCM - Local Path NA NA NA 1
R5F WKUP TCM - External Path 112 108 120 NA

Tests were done at 0.75V VDD_CORE settings (A53 : 1.25 GHz, C7x DSP: 1.0 GHz and R5: 800 MHz) and LPDDR4 @3200MT/s.