SPRAD93A February   2023  – October 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Using the Power Estimation Tool
    1. 1.1 Operating Performance Point (OPP)
    2. 1.2 Processor Core Utilization
    3. 1.3 LVCMOS IO
    4. 1.4 Peripherals
    5. 1.5 General
    6. 1.6 Estimated Power Consumption
  5. 2Revision History

1.1 Operating Performance Point (OPP)

This section allows the user to set the operating frequency of each of the compute cores and clusters.

  • A53: Bypass to 1400 MHz, depending on PLL resolution frequency step.
    Note: If using 1400 MHz, VDD_CORE should be set to 0.85 V, per the data sheet.
  • MCU R5F: Bypass to 800 MHz, depending on PLL resolution frequency step.
  • Device Manager R5F: 400 or 800 MHz, depending on PLL resolution frequency step.
  • M4F: 400 or 800 MHz, depending on PLL resolution frequency step.
  • C7x: Bypass to 1000 MHz
    Note: If using 1000 MHz, VDD_CORE should be set to 0.85 V, per the data sheet.
  • HSM: 133 or 400 MHz
  • VPAC: 187.5 or 375 MHz
  • VPU: 100, 200, or 400 MHz