The input voltage range of the embedded ADC in C2000 real-time microcontroller is limited to 3.3V. This can be sufficient for many applications. However, some applications, such as those using legacy industrial or automotive sensors, can require higher ADC input ranges, such as 5V or 12V. Depending on the application, there can be other design constraints, such as the input source not being able to drive the sampling capacitor of the SAR ADC. Another design concern can be the noise performance of the overall signal chain.

The simplest and lowest-cost method to attenuate a 5V or any other higher voltage signal to 3.3V is through a resistor divider network. Assume that there is an analog sensor that gives a 0-12V range signal. As shown in Figure 2-1, the user can employ a voltage divider with 36kΩ and 100kΩ resistors to bring a 12V sensor voltage down to a level less than 3.3V. However, selecting a Sample+Hold duration that is long enough for this circuit to achieve acceptable settling performance can be difficult. This issue necessitates using a unity-gain op-amp.

To address the issue of driving the SAR ADC from a high impedance source, the buffer mode is implemented in Type-2 PGA. A unity-gain op-amp with low output impedance can drive the resistor divider and provide isolation from the resistor divider and sampling capacitor. Moreover, the buffer mode is beneficial when a sensor has a high output impedance and is directly connected to an ADC for acquisition, then the resulting conversion result can be inaccurate due to the effects of the high impedance signal. Users can also use a filter resistor (100Ω) and capacitor (1nF) to form a low-pass filter with a cutoff frequency of 1.5MHz.

Note that when the PGA module is configured in a buffer mode, the designated inverting pin of the microcontroller (PGA_INM) is free to be used as general purpose I/O. Also, the Type-1 PGA module does not support the buffer mode.

For more information about driving circuit of the SAR ADC, you can refer to Charge Sharing Driving Circuits, application note which provides an excellent tutorial on how to select a source resistor and charge-sharing capacitor to drive an ADC.

Figure 2-1 Buffer Mode for a High-Impedance Source

The following code snippet shows where to add custom code to set the values for the M, N, and P-MUX to achieve buffer-mode operation, as well as selecting the appropriate filter resistor R_FILT connected internally to the output of the PGA module.

//
// Filter Resistor
//
#define PGA_FILTERVALUE PGA_LOW_PASS_FILTER_RESISTOR_100_OHM

//
// P-MUX selection
//
#define PGA_PMUXINPUT PGA_PMUX_POS
 
//
// N-MUX selection
//
#define PGA_NMUXINPUT PGA_NMUX_RTOP

//
// M-MUX selection
//
#define PGA_MMUXINPUT PGA_MMUX_NAKED_OPAMP

In the code snippet, PGA_FILTERVALUE represents the desired value for the filter resistor R_FILT. Please make sure to consult the documentation or reference manual for your specific device to find the available R_FILT values, and then replace PGA_FILTERVALUE with the actual value you want to use in your circuit.

Some applications can not tolerate having an RC network at the output of the amplifier. Amplifier output current flowing through the filter resistor creates a voltage offset that introduces output error. In this case, one can filter the noise spikes by placing a feedback capacitor across the feedback loop. This capacitor can compensate for the zero created by the feedback network and the input capacitance of the PGA module. Indeed, a simple single-pole low-pass filter can be implemented by placing an external capacitance between PGA_INM and PGA_OUT in internal gain mode, demonstrated in Figure 2-2. To enable this filter, set the PGA_FB_ON_PIN register to 1.

The cutoff frequency for this type of filter can be calculated by Equation 1.

Figure 2-2 Low-Pass Filter Using Embedded Gain Resistor R_ib and an External Capacitor