SPRADC1 june   2023 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Different Types of Memories on the TDA4VM
  5. 2Memory Overview and Intended Usage
    1. 2.1 PSROM
      1. 2.1.1 Typical Use Cases
    2. 2.2 PSRAM
      1. 2.2.1 Typical Use Cases
    3. 2.3 MSMC RAM
      1. 2.3.1 Typical Use Cases
      2. 2.3.2 Relevant Links
    4. 2.4 MSRAM
      1. 2.4.1 Typical Use Cases
    5. 2.5 ARM Cortex A72 Subsystem
      1. 2.5.1 L1/L2 Cache Memory
      2. 2.5.2 L3 Memory
      3. 2.5.3 Relevant Links
    6. 2.6 ARM Cortex R5F Subsystem
      1. 2.6.1 L1 Memory System
      2. 2.6.2 Cache
      3. 2.6.3 Tightly Coupled Memory (TCM)
      4. 2.6.4 Typical Use Case
      5. 2.6.5 Relevant Links
    7. 2.7 TI's C6x Subsystem
      1. 2.7.1 Memory Layout
      2. 2.7.2 Relevant Links
    8. 2.8 TI's C7x Subsystem
      1. 2.8.1 Memory Layout
      2. 2.8.2 Relevant Links
    9. 2.9 DDR Subsystem
      1. 2.9.1 Relevant Links
  6. 3Performance numbers
    1. 3.1 SDK Data Sheet
    2. 3.2 Memory Access Latency
  7. 4Software Careabouts When Using Different Memories
    1. 4.1 How to Modify Memory Map for RTOS Firmwares
    2. 4.2 DDR Sharing Between RTOS Core and HLOS
    3. 4.3 MCU On-Chip RAM Usage by Bootloader
    4. 4.4 MSMC RAM Default SDK Usage
      1. 4.4.1 MSMC RAM Reserved Sections
      2. 4.4.2 MSMC RAM Configuration as Cache and SRAM
    5. 4.5 Usage of ATCM from MCU R5F
    6. 4.6 Usage of DDR to Execute Code from R5F
  8. 5Summary

5 Summary

There are many memories available to software running on the Jacinto7 family of devices. Knowing where these memories are located, and how they are being used is important to system design.

While DDR memory is readily available to all cores, it is not always the most efficient selection. Amount of memory available must be weighed against performance of that memory, when choosing where to store information. These software architecture decisions can be unique for a particular core, but may also have an overall system impact.

Reviewing entire systems use of memory is recommended as part of design phase. TI’s Processor's E2E forum, is a great resource for any conversation on this subject.