SPRADC4 june   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2AM62A Processor
  6. 3Vision Pre-processing Accelerator (VPAC)
    1. 3.1 Vision Imaging Sub-System (VISS)
    2. 3.2 Lens Distortion Correction (LDC) Block
    3. 3.3 Multi-Scalar (MSC) Block
  7. 4Deep Learning Acceleration
  8. 5Camera Mirror System Data Flow and Latency
  9. 6End-to-End Functional Safety
  10. 7Example Demonstration
    1. 7.1 Hardware Equipment
    2. 7.2 Software Components
    3. 7.3 Latency Measurement
    4. 7.4 Future Improvement on Latency
  11. 8Summary
  12. 9References

7.4 Future Improvement on Latency

The demonstration described in Section 7.3 can achieve 60 ms glass-to-glass latency (not including deep learning related processing). A few improvements can be made to further reduce the latency:

  • Implementing the on-the-fly mode for VPAC, which can reduce the latency by either the camera data accumulation time or VISS processing time, whichever is shorter. For example, in the 2.1MP at 60 fps case, utilizing on-the-fly mode can reduce latency by the processing time of VISS which is 8 ms.
  • Removing MSC. The LDC block of VPAC can also resize the image, though LDC is not as flexible as MSC and LDC does not do anti-aliasing filtering. For certain applications, it is possible to just use LDC to resize the image without using MSC. In that case, the latency can be reduced by the MSC processing time, which is 8 ms for 2.1MP at 60 fps.