SPRADD4 October   2023 AM625SIP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Via Channel Arrays
  6. 3 Width/Spacing Proposal for Escapes
  7. 4 Stackup
  8. 5 Via Sharing
  9. 6 Floorplan Component Placement
  10. 7 Critical Interfaces Impact Placement
  11. 8 Routing Priority
  12. 9 SerDes Interfaces
  13. 10Power Decoupling
  14. 11Route Lowest Priority Interfaces Last
  15. 12Summary

4 Stackup

PCB stack-up is one of the first and important considerations in realizing a successful PCB. The AM62xSiP device supports a BGA array of 25 ˟ 25 with a 0.5-mm pitch and a body size of 13 mm. Due to the number of rows of signal balls around the periphery, TI recommends two routing layers. PDN compliance and robustness is critical to meet all the performance objectives of the device and associated peripherals. To enable this, TI recommends allocating two layers for power planes. Ground planes must be added adjacent to the power planes and adjacent to the outer layers for shielding and controlled impedance routing. High speed interfaces such as CSI, USB require ground planes for impedance matching. The escapes on the AM62xSiP board was achieved with 4 layers, as shown below.

Table 4-1 Example PCB Layer Stack-up
PCB Layer Layer Routing, Planes or Pours
Layer 1 Component pads and signal routing
Layer 2 Ground
Layer 3 Power
Layer 4 Signal Routing

The AM62xSiP board is implemented without HDI (High Density Interconnect) and does not use micro vias, which are both intended to save board cost. All vias on the AM62xSiP board are Plated Through Hole (PTH) and pass completely through the board. Proper analysis shall be performed to validate both signal and power integrity, if further optimizations are required to reduce PCB stack-up and/or routing rules illustrated in this document.