SPRADD4 October   2023 AM625SIP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Via Channel Arrays
  6. 3 Width/Spacing Proposal for Escapes
  7. 4 Stackup
  8. 5 Via Sharing
  9. 6 Floorplan Component Placement
  10. 7 Critical Interfaces Impact Placement
  11. 8 Routing Priority
  12. 9 SerDes Interfaces
  13. 10Power Decoupling
  14. 11Route Lowest Priority Interfaces Last
  15. 12Summary

5 Via Sharing

The Via Channel Array BGA pattern implemented on the AM62xSiP design offers several opportunities for via sharing. Vias are shared across BGA pins. Figure 5-1 and Figure 5-2 show the via sharing opportunities for VDD_CORE and VSS power supplies, respectively. Via sharing across BGA pins provides for easier escape routing and robust electrical connection by connecting multiple pins.

GUID-7F251A92-61E1-47BE-8686-CDF169360DE2-low.png Figure 5-1 Via Sharing for VDD_CORE Domain
GUID-9EF9AE76-C604-4AE1-9147-BAACE404BBED-low.png Figure 5-2 Via Sharing for VSS