2 Implementation

Microcontroller without flexible external logic can uses software to communication with the external device via its general-purpose input/output (GPIO) to simulate protocol or to drive some outputs with a certain waveform. Chip infrastructure like a Network on Chip (NOC) exists between the CPU cores and the GPIO pins and also with pipeline. The pattern is written from the CPU’s internal registers through the NOC infrastructure to reach the GPIO. The NOC can add tens to even hundreds of nanoseconds of latency and jitter to the GPIO write commands. The system might not meet the peripheral’s timing requirements for the output signal duty cycle, the relationship between outputs. These and other factors mean that compared to an FPGA, a standard MCU will have increased latency and lower determinism when interacting with a GPIO.

TI’s PRU core is a best-in-class custom CPU designed to have the lowest latency and highest determinism in GPIO reads & writes. The PRU has 32 general purpose register inside the core and two registers are connected to general purpose output or input directly, which means that PRU core can access to external pin at single cycle. Since there is no NOC circuitry between the registers and the pins, signal latency from the core to the processor pins is dramatically reduced. Output signal jitter due to the signal path is 100% removed. The PRU gives best in class performance without losing flexibility.

This application only focuses on PRU_ICSSG. Each PRU_ICSSG actually has six cores, three cores in each slice. So, an AM243x or AM64x with two PRU_ICSSG subsystems will have 12 cores total. For more information, see the PRU_ICSSG section from the AM64x/AM243x Technical Reference Manual.

As shown in Figure 2-1, The general register R30 and R31 can be routed directly to the PRU’s dedicated general purpose input (PRU GPI) and general-purpose output (PRU GPO). GPI signals and system events or interrupts to the PRU can be read by reading the R31 register, while the PRU can release system events by writing to the R31 register. Similarly, writing to the R30 register performs writes to the dedicated PRU GPO pins.

The PRU implements an enhanced General-Purpose Input/output (GPIO) module with system control units that supports the following GPI and GPO modes: direct input/output, 16-bit parallel capture, 28-bit serial shift in/shift out, and MII_RT. Table 2-1 describes the input/output modes in detail.

The PRUx_R31_status [0:19] bits of the internal PRU register file are mapped to device-level, general purpose input pins (PRUx_GPI [0:19]). In GPI Direct Input mode, PRU0_GPI [0:19] feeds directly to PRUx_R31_status [0:19]. For example, instruction “ldi R10.b0, R31.b0” can shift data on the PRUx_GPI [0:7] lane into the first byte of R10 in a single PRU core cycle.

The following sections show how to customize the serial and parallel port through GPIO direct mode. For the serial port, transmission of data is simulated through the GPO pin, for example, the GPO pin status depends on the corresponding bit of the data register.