1 Introduction

Many medical equipment designs need low latency communication, or custom communication protocols. TI’s Sitara processors with programmable real-time unit (PRU) cores are designed to meet those needs without having to add additional field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), complex programmable logic device (CPLD) to the design.

Some potential use cases include:

Clinical monitoring equipment has many types of monitoring parameters, like Electrocardiography (ECG), Electromyography (EMG), Oxyhemoglobin saturation by pulse oximetry (SpO2), temperature, and bioelectrical impedance. However, there are often real-time requirements for the refresh rate of those parameters. Those real-time needs may require non-standard interfaces or protocols between the multi-parameter module and the main board.

In imaging systems, Continuous Wave (CW) Doppler is used to measure the blood flow inside the human body. The demodulated Doppler frequency produces in-phase (I) and quadrature (Q) data as outputs. Analog-to-digital converters (ADCs) are required to support a simultaneous sampling rate over 3MHz with 14-16-bit accuracy. The ADC output is often parallel CMOS or enhanced SPI. The analog front-end readout electronics required for direct imaging to convert a charge to digital data in an X-ray flat panel detector (FPD). The digital signal processor (DSP), FPGAs, ASICs or a combination of these applies signal conditioning. These processors also manage high-speed serial or parallel communications with the external image-processing unit through a high-speed interface.

In a vitro Polymerase Chain Reaction (PCR) detection system, samples are excited by a multi-band light source. Multiple analog signals from fluorescence detection signal chains need to be captured on a single processor for further processing. When more than two ADCs need to be interfaced with processor, processors with multiple SPI interfaces have limited access to more than two ADCs simultaneously due to sharing of the same SPI DMA data path. The PRU allows for simultaneous access to multiple ADCs. For more information, see the Flexible Interface (PRU-ICSS) Reference Design for Simultaneous, Coherent DAQ Using Multiple ADCs Design Guide.

In these application scenarios, most pipelined CPU processors have a fundamental drawback compared to FPGA or CPLD: the pipelined processors have higher latency and higher jitter. FPGA or CPLD flexibility and low latency are well suited to these scenarios, but adding FPGAs increase complexity and system cost. TI’s Sitara processors with PRU cores are designed to suit these scenarios without the need to add FPGAs, CPLDs to the design. This application note demonstrates how the PRU’s ultra-fast general-purpose input/output (GPIO), board-side RAM, and shift out/in peripherals enable high-speed, customized communication over serial or parallel interfaces.