SPRADF0A November   2023  – November 2023 AM263P2 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Why External on-PCB Flash?
  5. 2OptiFlash Detailed Overview
    1. 2.1 OptiFlash System KPIs Key Performance Indices
  6. 3Summary
  7. 4References
  8. 5Revision History

2.1 OptiFlash System KPIs Key Performance Indices

A direct comparison of embedded flash MCU devices to OptiFlash devices is not relevant as overall architectures are different. Yet, as mentioned previously, both require application developers to execute time-critical code from on-chip memory to meet necessary processing timelines. To show how this balance of flash and on-chip memory performance can be achieved, TI has developed a set of system KPIs that measure OptiFlash performance and its constituent accelerators and tools. Following KPIs are being measured using application-1 that emulates a poorly cached AutoSAR application, and Application-2, which is a real-world networking example with Lwip client-server + Mbed TLS use case.

Table 2-1 DMIPS Loss With and Without OptiFlash RL2
Test KPI Without OptiFlash OptiFlash Enabled App. Use case
XIP Basic (without Safety Security) CPU DMIPs loss of 2-3x observed DMIPs degradation limited to 1.1x with 128kB RL2. App-1 and App-2
W/ Safety and Security DMIPs degradation limited to 1.4x with Hardware accelerators for in-line ECC and OTFA. App-1 and App-2
Note: In the above results, the “with safety and security” scenario includes in-line error-correction-code (ECC) and on-the-fly-authentication (OTFA).

Table 2-2 show the impact of the configurable RL2 cache. A cache size larger than 128KB did not show further improvement in XIP performance. The optimal RL2 cache size also eliminated the difference in processing timelines with and without security and safety. Note that degradation is in comparison of internal RAM. For example, when L2 cache was disabled, application performed 2.4 times worst when run from external flash in comparison to internal RAM.

Table 2-2 Impact of the Configurable RL2 Cache
Test/ Cache Size Used (kB) Performance Degradation With Safety and Security Performance Degradation Without Safety and Security App. Use Case
RL2 access size 0 2.4x 2.2x App-1
16 2.2x 1.9x
32 1.9x 1.7x
128 1.1x 1.1x

The Smart Placement tool was used to analyze the application and place time-sensitive code or data in TCM, OCRAM, or flash. Table 2-3 showed that the Smart Placement Tool enabled 19% application execution time improvement when utilized for both code and data.

Table 2-3 Impact of Smart Placement Tool on App1
Test/ TCM Size Used (kB) Data vs. Code Execution Time (μS) % Improvement With Smart Placement App Use Case
Execution time improved with Smart Placement 0 n/a 27,583 N/A App 1
64 code 25,342 9%
64 code + data 22,537 19%

In another OptiFlash XIP test, an EtherNet/IP protocol application was implemented with XIP mode and then with XIP using the Smart Placement tool. As can be seen, the CPU loading was reduced and the worst-case jitter was notably improved with Smart Placement.

Table 2-4 Impact of Smart Placement Tool on OOB EtherNet/IP Protocol Application
Test Max. CPU Loading (%) Worst case jitter App. Use case
XIP 98.91 115.7 EtherNet/IP protocol application
XIP + Smart Placement 85.97 (13% better) 68 (40% better)

The OptiShare technology was used to optimize code sharing among R5F cores for an IPC application on the MCU+ SDK. When using OptiShare, the code size was reduced by 10%.

Table 2-5 Impact of OptiShare on OOB IPC Example
Test Code Size (kB) Memory Footprint Optimized (%) App. Use Case
Code size reduction with OptiShare 73 ~10 (lower code size) SDK Out-of-box IPC application