SPRADG4A January   2024  – April 2024

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  5. 2Introduction
  6. 3System Description
    1. 3.1 Key System Specifications
  7. 4System Overview
    1. 4.1 Block Diagram
    2. 4.2 Basic Operation
    3. 4.3 System Design Theory
      1. 4.3.1 Peak Current Mode Control (PCMC) Implementation
      2. 4.3.2 Zero Voltage Switching (ZVS) or Low Voltage Switching (LVS)
      3. 4.3.3 Synchronous Rectification
      4. 4.3.4 Slope Compensation
  8. 5Hardware
    1. 5.1 Hardware Overview
    2. 5.2 Hardware and Test Instruments Required
    3. 5.3 TMDSCNCD263 controlCARD™ Changes
  9. 6Software
    1. 6.1 Getting Started With Firmware
      1. 6.1.1 Opening the Code Composer Studio Project
      2. 6.1.2 Software Architecture
      3. 6.1.3 Project Folder Structure
    2. 6.2 SysConfig Setup
      1. 6.2.1 EPWM Configuration
      2. 6.2.2 ADC Configuration
      3. 6.2.3 CMPSS Configuration
    3. 6.3 Incremental Builds
      1. 6.3.1 Procedure for Running the Incremental Builds - PCMC
        1. 6.3.1.1 Lab 1: Phase Overlapping Check With Open Current and Voltage Loop
          1. 6.3.1.1.1 Objective of Lab 1
          2. 6.3.1.1.2 Overview of Lab 1
          3. 6.3.1.1.3 Procedure of Lab 1
            1. 6.3.1.1.3.1 Start CCS and Open a Project for Lab 1
            2. 6.3.1.1.3.2 Build and Load the Project for Lab 1
            3. 6.3.1.1.3.3 Debug Environment Windows for Lab 1
            4. 6.3.1.1.3.4 Run the Code for Lab 1
        2. 6.3.1.2 Lab 2: Closed Current and Open Voltage Loop
          1. 6.3.1.2.1 Objective of Lab 2
          2. 6.3.1.2.2 Overview of Lab 2
          3. 6.3.1.2.3 Procedure of Lab 2
            1. 6.3.1.2.3.1 Build and Load Project for Lab 2
            2. 6.3.1.2.3.2 Debug Environment Windows for Lab 2
            3. 6.3.1.2.3.3 Run the Code for Lab 2
        3. 6.3.1.3 Lab 3: Closed Current and Closed Voltage Loop
          1. 6.3.1.3.1 Objective of Lab 3
          2. 6.3.1.3.2 Overview of Lab 3
          3. 6.3.1.3.3 Procedure of Lab 3
            1. 6.3.1.3.3.1 Build and Load Project for Lab 3
            2. 6.3.1.3.3.2 Debug Environment Windows for Lab 3
            3. 6.3.1.3.3.3 Run the Code for Lab 3
  10. 7Testing and Results
    1. 7.1 Lab 0: Basic PWM Check
    2. 7.2 Lab 1: Phase Overlapping Check With Open Current and Voltage Loop
    3. 7.3 Lab 2: Closed Current and Open Voltage Loop
    4. 7.4 Lab 3: Closed Current and Closed Voltage Loop
  11. 8References
  12. 9Revision History

4.3.3 Synchronous Rectification

GUID-15EC973E-3BB6-4E7F-8B2B-C3703D6EE3CE-low.gif Figure 4-5 Synchronous Rectification Mode

Synchronous rectifiers can work in one of the following three modes at any given time:

  • Mode 0: This is the classical diode current doubler mode achieved by keeping synchronous rectifiers turned OFF. It is useful for very low load operations where synchronous rectifier switching losses are greater than the power savings obtained by synchronous rectification.
  • Mode 1: In this mode the synchronous rectifier switches behave like ideal diodes. This mode is useful when operating at very low to low loads, typically when burst mode is being used. In this mode, synchronous rectifier MOSFETs are ON only when the corresponding diagonal bridge drive signals overlap.
  • Mode 2: Useful for all other load conditions. In this mode, synchronous rectifier MOSFETs are OFF only when the corresponding opposite diagonal bridge drive signals overlap.

Figure 4-5 depict waveforms generated for driving the synchronous rectifier switches in these modes. It is important to implement mode transitions seamlessly without any glitches or anomalies on the PWM outputs even during large load transients or sudden phase shift change commands to provide safe operation of the system.