SPRADG4A January   2024  – April 2024

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  5. 2Introduction
  6. 3System Description
    1. 3.1 Key System Specifications
  7. 4System Overview
    1. 4.1 Block Diagram
    2. 4.2 Basic Operation
    3. 4.3 System Design Theory
      1. 4.3.1 Peak Current Mode Control (PCMC) Implementation
      2. 4.3.2 Zero Voltage Switching (ZVS) or Low Voltage Switching (LVS)
      3. 4.3.3 Synchronous Rectification
      4. 4.3.4 Slope Compensation
  8. 5Hardware
    1. 5.1 Hardware Overview
    2. 5.2 Hardware and Test Instruments Required
    3. 5.3 TMDSCNCD263 controlCARD™ Changes
  9. 6Software
    1. 6.1 Getting Started With Firmware
      1. 6.1.1 Opening the Code Composer Studio Project
      2. 6.1.2 Software Architecture
      3. 6.1.3 Project Folder Structure
    2. 6.2 SysConfig Setup
      1. 6.2.1 EPWM Configuration
      2. 6.2.2 ADC Configuration
      3. 6.2.3 CMPSS Configuration
    3. 6.3 Incremental Builds
      1. 6.3.1 Procedure for Running the Incremental Builds - PCMC
        1. 6.3.1.1 Lab 1: Phase Overlapping Check With Open Current and Voltage Loop
          1. 6.3.1.1.1 Objective of Lab 1
          2. 6.3.1.1.2 Overview of Lab 1
          3. 6.3.1.1.3 Procedure of Lab 1
            1. 6.3.1.1.3.1 Start CCS and Open a Project for Lab 1
            2. 6.3.1.1.3.2 Build and Load the Project for Lab 1
            3. 6.3.1.1.3.3 Debug Environment Windows for Lab 1
            4. 6.3.1.1.3.4 Run the Code for Lab 1
        2. 6.3.1.2 Lab 2: Closed Current and Open Voltage Loop
          1. 6.3.1.2.1 Objective of Lab 2
          2. 6.3.1.2.2 Overview of Lab 2
          3. 6.3.1.2.3 Procedure of Lab 2
            1. 6.3.1.2.3.1 Build and Load Project for Lab 2
            2. 6.3.1.2.3.2 Debug Environment Windows for Lab 2
            3. 6.3.1.2.3.3 Run the Code for Lab 2
        3. 6.3.1.3 Lab 3: Closed Current and Closed Voltage Loop
          1. 6.3.1.3.1 Objective of Lab 3
          2. 6.3.1.3.2 Overview of Lab 3
          3. 6.3.1.3.3 Procedure of Lab 3
            1. 6.3.1.3.3.1 Build and Load Project for Lab 3
            2. 6.3.1.3.3.2 Debug Environment Windows for Lab 3
            3. 6.3.1.3.3.3 Run the Code for Lab 3
  10. 7Testing and Results
    1. 7.1 Lab 0: Basic PWM Check
    2. 7.2 Lab 1: Phase Overlapping Check With Open Current and Voltage Loop
    3. 7.3 Lab 2: Closed Current and Open Voltage Loop
    4. 7.4 Lab 3: Closed Current and Closed Voltage Loop
  11. 8References
  12. 9Revision History

Basic Operation

A PSFB converter consists of four-power electronic switches (like MOSFETs or IGBTs) that form a full-bridge on the primary side of the isolation transformer and diode rectifiers or MOSFET switches for synchronous rectification (SR) on the secondary side. This topology allows the switching devices to switch with zero voltage switching (ZVS) resulting in lower switching losses and an efficient converter.

For such an isolated topology, signal rectification is required on the secondary side. For systems with low output voltage and/or high output current ratings, implementing synchronous rectification instead of diode rectification achieves the best possible performance by avoiding diode rectification losses. In this work, synchronous rectification is implemented on the secondary side.

GUID-20201007-CA0I-M0MH-XMCS-FQZL59529MPS-low.gif Figure 4-2 A Phase-Shifted Full Bridge Circuit

Figure 4-2 shows a simplified circuit of a phase shifted full-bridge. MOSFET switches Q1, Q4, Q2 and Q3 form the full-bridge on the primary side of the transformer T1. Q1 and Q4 are switched at 50 % duty and 180° out of phase with each other. Similarly, Q2 and Q3 are switched at 50 % duty and 180° out of phase with each other. The PWM switching signals for leg Q2 – Q3 of the full-bridge are phase shifted with respect to those for leg Q1 - Q4. Amount of this phase shift decides the amount of overlap between diagonal switches, which in turn decides the amount of energy transferred. D5, D6 provide diode rectification on the secondary(MOSFETs used in our design for SR), while Lo and Co form the output filter. Shim inductor LR provides assistance to the transformer leakage inductance for resonance operation with MOSFET capacitance and facilitates Zero Voltage Switching (ZVS). The switching waveforms for the system are shown in Figure 4-3.

GUID-3245FE21-DFED-4AC8-96F1-04197921C33A-low.gif Figure 4-3 PSFB PWM Waveforms