SPRADH2A February   2024  – November 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1 , DS90UB953A-Q1 , DS90UB960-Q1 , TDES960 , TSER953

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Connecting Multiple CSI-2 Cameras to the SoC
    1. 2.1 CSI-2 Aggregator Using SerDes
    2. 2.2 CSI-2 Aggregator without Using SerDes
    3. 2.3 Supported Camera Data Throughput
  6. 3Enabling Multiple Cameras in Software
    1. 3.1 Camera Subsystem Software Architecture
    2. 3.2 Image Pipeline Software Architecture
  7. 4Reference Design
    1. 4.1 Supported Cameras
    2. 4.2 Setting up Four IMX219 Cameras
    3. 4.3 Configuring Cameras and CSI-2 RX Interface
    4. 4.4 Streaming from Four Cameras
      1. 4.4.1 Streaming Camera Data to Display
      2. 4.4.2 Streaming Camera Data through Ethernet
      3. 4.4.3 Storing Camera Data to Files
    5. 4.5 Multicamera Deep Learning Inference
      1. 4.5.1 Model Selection
      2. 4.5.2 Pipeline Setup
  8. 5Performance Analysis
  9. 6Summary
  10. 7References
  11. 8Revision History

2.3 Supported Camera Data Throughput

The total supported data throughput of all connected cameras depends on the CSI-2 bandwidth and the ISP bandwidth.

  • For the AM6x devices that do not have an ISP such as AM62P, the CSI-2 bandwidth, 1.5Gbps per lane or 6Gbps for 4 lanes, is the limiting factor. As long as the total data bandwidth of all cameras is below 6Gbps, this can be supported.
  • For the AM6x devices with an ISP such as AM62A, the ISP bandwidth is the limiting factor. The ISP bandwidth of the AM62A is 315MPixel/s. As long as the total data rate of all cameras is below 315MPixel/s (regardless of the raw data bit-depth), this can be supported. The total supported camera data throughput also depends on system load such as DDR bandwidth. The Performance Analysis section presents the DDR usage for a specific example as a reference.