SPRADH8 September   2024 AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 AM64x and AM243x EVMs
    2. 1.2 SoC Architecture
      1. 1.2.1 AM64x
      2. 1.2.2 AM243x
    3. 1.3 Peripherals
      1. 1.3.1 CPSW3G
      2. 1.3.2 PRU-ICSSG
    4. 1.4 Ethernet Software Architecture
    5. 1.5 Prerequisite
      1. 1.5.1 HW Prerequisite
      2. 1.5.2 SW Prerequisite
        1. 1.5.2.1 Resource Allocation - AM64x
        2. 1.5.2.2 SBL update
  5. 2 Multicore 5-Ethernet Ports Realization
  6. 3 Supported Configurations on PRU-ICSSG
  7. 4 Implementation
    1. 4.1 System Example
      1. 4.1.1 Software Architecture
      2. 4.1.2 5-Ethernet Port Example
  8. 5 Debug Steps
  9. 6 Reference Logs
  10. 7 Testing for the ICSSG0 and ICSSG1 Functionality
  11. 8 ICSSG and CPSW
  12. 9 Summary
  13. 10References

1.5.2.1 Resource Allocation - AM64x

Resource manager must be asked first to allocate any peripheral to any core. Users can configure ICSSG0, ICSSG1 and CPSW Ethernet ports with different modes (MII, RMII, RGMII) using sysconfig tool and attach to the core as per need.

CAUTION:

These are the examples given for AM64x which has A53 core:

AM243x does not have A53 core.

Use resource allocation as per use case.

Use the following steps to enable this feature:

  1. Navigate to the MCU-PLUS-SDK installation directory (In this document, this is referred to as MCU_SDK_HOME).
    For example: C:\ti\mcu_plus_sdk_am64x_09_01_00_41
  2. Open the command prompt and run the following command:
    gmake -s -C tools/sysfw/boardcfg configure SOC=am64x
  3. Change the Tx and Rx channel count for CPSW, ICSSG0, and ICSSG1 to 0 in the A53 core.
    AM6442 SysConfig: Packet DMAFigure 1-6 SysConfig: Packet DMA
  4. After the channel counts are updated, the values are as follows:
    • CPSW Tx channel count = 0
    • CPSW Rx channel count = 0
    • ICSSG0 Tx channel count = 0
    • ICSSG0 Rx channel count = 0
    • ICSSG1 Tx channel count = 0
    • ICSSG1 Rx channel count = 0
    AM6442 SysConfig: Packet DMA Ring AcceleratorFigure 1-7 SysConfig: Packet DMA Ring Accelerator
    • Rings for CPSW Tx channel count = 0
    • Rings for CPSW Rx channel count = 0
    • Rings for CPSW Rx flows count = 0
    • Rings for ICSSG0 Tx channel count = 0
    • Rings for ICSSG0 Rx channel count = 0
    • Rings for ICSSG0 Rx flows count = 0
    • Rings for ICSSG1 Tx channel count = 0
    • Rings for ICSSG1 Rx channel count = 0
    • Rings for ICSSG1 Rx flows count = 0
  5. From (0,0) to (8,1) in R5-non secure 0-1 core (main-0-r5-0-1).
  6. Change resource sharing from A52 -> r5_ss_0-1 to r5_ss_0-1 -> r5_ss_0-3.
  7. gmake -s -C tools/sysfw/boardcfg configure-gen SOC=am64x
  8. Navigate to the following file.
    source/drivers/sciclient/sciclient_default_boardcfg/am64x/sciclient_defaultBoardcfg_rm.c
  9. Change the core allocations from A53 -> r5_ss_0-1 to r5_ss_0-1 -> r5_ss_0-3 for CPSW-related changes. There are three A53 changes and three r5-0-1 changes.