SPRADH9 June   2024 AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Abbreviations
  5. 2Introduction
    1. 2.1 Peripheral Component Interconnect Express
      1. 2.1.1 Components of PCIe Communication
        1. 2.1.1.1 Root Complex
        2. 2.1.1.2 Repeater
        3. 2.1.1.3 Endpoints
      2. 2.1.2 Signaling
        1. 2.1.2.1 PERST
        2. 2.1.2.2 WAKE and CLKREQ
        3. 2.1.2.3 REFCLK
      3. 2.1.3 PCIe Common Usage
      4. 2.1.4 PCIe Aggregate Throughput
    2. 2.2 PCIe Features on AM64x and AM243x
  6. 3X86 as RC and AM64x as EP
    1. 3.1 Hardware Environment
    2. 3.2 Software Environment
      1. 3.2.1 Building Application
      2. 3.2.2 Usage
  7. 4Test Setup
    1. 4.1 Common Setup for LINUX and WIN
    2. 4.2 Linux Driver (VFIO)
      1. 4.2.1 Prerequisites
      2. 4.2.2 Building
      3. 4.2.3 Deploying
    3. 4.3 Test Application Usage
    4. 4.4 Setup Steps for LINUX PC
      1. 4.4.1 UART Console Output
    5. 4.5 MSI Example
    6. 4.6 Setup Steps for WINDOWS PC
      1. 4.6.1 Prerequisites
      2. 4.6.2 Building
      3. 4.6.3 Deploying
  8. 5PCIe Test Specification
    1. 5.1  Identification and Configuration Functionalities
      1. 5.1.1 Test Case
    2. 5.2  Reference Clock Functionalities
    3. 5.3  Inbound ATU and BAR Functionalities
    4. 5.4  Outbound ATU Functionalities
    5. 5.5  MSI Functionality
    6. 5.6  Downstream Interrupt Functionality
    7. 5.7  Device Power Management State Functionality
    8. 5.8  Function Level Reset Mechanism
    9. 5.9  Legacy Interrupt Mechanism
    10. 5.10 MSI-X Capability
    11. 5.11 Hot Reset Mechanism
  9. 6Windows Example Driver Verification
  10. 7References

2.1.1 Components of PCIe Communication

PCIe communication consists of three main components: root complex, repeaters, and PCIe endpoints. PCIe communication is hierarchical so there is a single source, which is the root complex, through which all the data passes. The data goes to the root complex from multiple PCIe endpoints and vice versa.

AM6442 PCIe Topology Figure 2-1 PCIe Topology