SPRADJ1A June   2024  – August 2024 TMS320F280021 , TMS320F280023 , TMS320F280023C , TMS320F280025 , TMS320F280025C , TMS320F280033 , TMS320F280034 , TMS320F280037 , TMS320F280037C , TMS320F280039 , TMS320F280039C , TMS320F280041 , TMS320F280041C , TMS320F280045 , TMS320F280049 , TMS320F280049C , TMS320F28075 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377S , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379S , TMS320F28P550SJ , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2HHC LLC Control Architecture and Logic Diagram
    1. 2.1 CMPSS
    2. 2.2 EPWM
    3. 2.3 Configurable Logic Block (CLB)
  6. 3C2000 Configurations in HHC LLC
    1. 3.1 CMPSS Configurations
    2. 3.2 EPWM Configurations
    3. 3.3 CLB Configurations
  7. 4System Control Method
    1. 4.1 Soft Start
    2. 4.2 Burst Mode Control
    3. 4.3 Minimum and Maximum Frequency Clamping
  8. 5Resonant Capacitor Voltage Sensing Design
  9. 6Summary
  10. 7References
  11. 8Revision History

2 HHC LLC Control Architecture and Logic Diagram

Figure 2-1 is a simplified schematic diagram of an LLC converter with HHC scheme. Compared to the voltage mode control, it is required to sense the voltage of resonant capacitor (VCR) and control the swing amplitude for HHC, which works as an inner loop in addition to the voltage control loop. Similar to the peak current control, the VCR control is used to controlling the energy transferred from resonant tank to the output for LLC. For the VCR sensing circuits, it can also leverage the existed current sense transformer, which is explained in the later section.

HHC LLC Schematic Diagram Figure 2-1 HHC LLC Schematic Diagram

Figure 2-2 shows the HHC control architecture within the C2000 MCU, which includes the outer voltage loop and hardware-based VCR loop. The voltage loop compensator generates the control value to the ramp generator of comparator subsystem module (CMPSS), based on the error from sensed voltage and reference voltage. The CMPSS compares the sensed VCR voltage with the ramp generator value, and generates events to control the PWM signal for the high side FET. CLB is used to create the PWM signal for the low side FET with a specific logic from the high side PWM.

HHC LLC Control Architecture Figure 2-2 HHC LLC Control Architecture

Different from the traditional peak current mode control on buck, boost or phase shift full bridge topologies, which run with fixed switching frequency, while HHC LLC implements the peak current mode control for variable switching condition. Figure 2-2 shows the HHC switching waveform. When the VCR voltage swings up and comparator event is triggered, the high side FET can be turned off, and the low side FET can be turned on. In the later half cycle, the low side FET’s on-time is kept as the same as the high side FET’s. Similar with peak current mode control, a compensating slope is added to keep the control loop stable during the light load, when the VCR swing amplitude is very small.

Block Diagram of the System Control Logic Within C2000 Figure 2-3 Block Diagram of the System Control Logic Within C2000

Figure 2-3 shows the block diagram of the HHC control logic, which mainly includes three peripherals of C2000.