SPRADJ9 August   2024 AM62P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2AM62Px Processor
    1. 2.1 Key Features and Benefits
    2. 2.2 AM62P Display Subsystem
    3. 2.3 AM62P Display Subsystem Clocking Architecture
  6. 3Display Signals and Timing Parameters
  7. 4Steps for Integration (Linux®)
    1. 4.1 Linux® Overlay File
    2. 4.2 Timing Information
  8. 5Steps for Integration (RTOS)
  9. 6Terminology

5 Steps for Integration (RTOS)

Integrate a new LVDS panel in RTOS using this SysConfig configurator which is part of the MCU_PLUS_SDK. The sysconfig for the DSS driver provides the following configuration tabs to integrate a new LVDS panel.

  1. Video Port Timing Configuration:
    • Configure the Pixel Clock Frequency required for the panel
    • Timing parameters HSYNC, VSYNC, VFP, VBP, HFP, HBP and more
    • Interface width: 24 bit or 18 bit
    • Timing signals polarity
  2. OLDI Configuration:
    • Map type for OLDI: VESA, JEIDA, 24-bit or 18-bit standards
    • Input bit width: Whether panel connected expects 24-bit or 18-bit input
    • Dual link mode: Enable or disable dual-link mode
    • Data enable signal polarity

AM62P SysConfig Configurator

Figure 5-1 SysConfig Configurator