SPRADO2 November   2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Application Note Usage Guidelines
      1. 1.1.1 Processor Family Specific Application Note
      2. 1.1.2 Schematics Design Guidelines
      3. 1.1.3 Schematic Review Checklist
      4. 1.1.4 FAQ Reference for Application Note Usage Guidelines
    2. 1.2 AM62Ax Processor Family
      1. 1.2.1 AM62A7
      2. 1.2.2 AM62A7-Q1
      3. 1.2.3 AM62A3
      4. 1.2.4 AM62A3-Q1
  5. 2 Related Collaterals
    1. 2.1 Links to Commonly Available and Applicable Collaterals
    2. 2.2 Hardware Design Considerations for Custom Board
  6. 3 Processor Selection
    1. 3.1 Data Sheet Use Case and Version References in the Application Note
    2. 3.2 Device Selection and OPN
    3. 3.3 Peripheral Instance Naming Convention
    4. 3.4 Unused Peripherals
    5. 3.5 Processor Ordering and Quality
    6. 3.6 Processor Selection Checklist
  7. 4 Power Architecture
    1. 4.1 Generating Supply Rails
      1. 4.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
        1. 4.1.1.1 PMIC
          1. 4.1.1.1.1 PMIC Checklist
          2. 4.1.1.1.2 Additional References
        2. 4.1.1.2 Discrete Power
          1. 4.1.1.2.1 DC/DC Converter
          2. 4.1.1.2.2 LDO
          3. 4.1.1.2.3 Discrete Power Checklist
    2. 4.2 Power Control and Circuit Protection
      1. 4.2.1 Load Switch (Power Switching)
        1. 4.2.1.1 Load Switch Checklist
      2. 4.2.2 eFuse IC (Power Switching and Protection)
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (SK - Starter Kit)
      1. 5.1.1 Evaluation Module Checklist
    2. 5.2 Device-Specific (Processor-Specific, Processor-Family Specific) SK Versus Data Sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Pull Resistor
        3. 5.2.1.3 Drive Strength Configuration
        4. 5.2.1.4 Data Sheet Recommendations
        5. 5.2.1.5 Processor IOs - External ESD Protection
        6. 5.2.1.6 Peripheral Clock Output Series Resistors
        7. 5.2.1.7 Component Selection Checklist
      2. 5.2.2 Additional Information Regarding Reuse of SK Design
        1. 5.2.2.1 Updated SK Schematic With Design, Review and CAD Notes Added
          1. 5.2.2.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
        2. 5.2.2.2 SK Design Files Reuse
          1. 5.2.2.2.1 Reuse of SK Design Checklist
    3. 5.3 Before Beginning the Design
      1. 5.3.1  Documentation
      2. 5.3.2  Processor Pin Attributes (Pinout) Verification
      3. 5.3.3  Device Comparison and IOSET
      4. 5.3.4  RSVD Reserved Pins (Signals)
      5. 5.3.5  Note on PADCONFIG Registers
      6. 5.3.6  Processor IO (Signal) Isolation for Fail-Safe Operation
      7. 5.3.7  Reference to Device-Specific SK
      8. 5.3.8  High-Speed Interface Design Guidelines
      9. 5.3.9  Recommended Current Source or Sink for LVCMOS (GPIO) Outputs
      10. 5.3.10 Connection of Slow Ramp Inputs or Capacitors to LVCMOS IOs (Inputs or Outputs)
      11. 5.3.11 Queries and Clarifications Related to Processor During Custom Board Design
      12. 5.3.12 Before Beginning the Design Checklist
      13. 5.3.13 Device Recommendations
  9. 6 Processor-Specific Recommendations
    1. 6.1 Common (Processor Start-Up) Connection
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Supply for Core and Peripherals
          1. 6.1.1.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
          2. 6.1.1.1.2 Additional Information
          3. 6.1.1.1.3 Processor Core and Peripheral Core Power Supply Checklist
          4. 6.1.1.1.4 Peripheral Analog Power Supply Checklist
        2. 6.1.1.2 Supply for IO Groups
          1. 6.1.1.2.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
          2. 6.1.1.2.2 Additional Information
          3. 6.1.1.2.3 Supply for IO Groups Checklist
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
          1. 6.1.1.3.1 VPP Checklist
        4. 6.1.1.4 Supply Connection for Partial IO Mode (Low-Power) Configuration
          1. 6.1.1.4.1 Partial IO Used
          2. 6.1.1.4.2 Partial IO Unused
          3. 6.1.1.4.3 Data Sheet Reference for Power Sequence
          4. 6.1.1.4.4 Partial IO Low Mode Checklist
        5. 6.1.1.5 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
        2. 6.1.2.2 Additional Information
          1. 6.1.2.2.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
        3. 6.1.2.3 Capacitors for Supply Rails Checklist
      3. 6.1.3 Processor Clock
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 High Frequency Oscillator (MCU_OSC0_XI / MCU_OSC0_XO)
          2. 6.1.3.1.2 Low Frequency Oscillator (WKUP_LFOSC0_XI / WKUP_LFOSC0_XO)
          3. 6.1.3.1.3 EXT_REFCLK1 (External Clock Input to Main Domain)
          4. 6.1.3.1.4 Additional Information
          5. 6.1.3.1.5 Clock Input Checklist - MCU_OSC0
          6. 6.1.3.1.6 Clock Input Checklist - WKUP_LFOSC0
        2. 6.1.3.2 Clock Outputs
          1. 6.1.3.2.1 Clock Output Checklist
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 External Reset Inputs
        2. 6.1.4.2 Reset Status Outputs
        3. 6.1.4.3 Additional Information
        4. 6.1.4.4 Processor Reset Input Checklist
        5. 6.1.4.5 Processor Reset Status Output Checklist
      5. 6.1.5 Configuration of Boot Modes (for Processor)
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Boot Mode Selection
          1. 6.1.5.2.1 Notes for USB Boot Mode
        3. 6.1.5.3 Boot Mode Implementation Approaches
        4. 6.1.5.4 Additional Information
        5. 6.1.5.5 Configuration of Boot Modes (for Processor) Checklist
    2. 6.2 Board Debug Using JTAG and EMU
      1. 6.2.1 JTAG and EMU Used
      2. 6.2.2 JTAG and EMU Not Used
      3. 6.2.3 Additional Information
      4. 6.2.4 Board Debug Using JTAG and EMU Checklist
  10. 7 Processor Peripherals
    1. 7.1 Supply Connections for IO Groups
      1. 7.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
      2. 7.1.2 Supply Connections for IO Groups Checklist
    2. 7.2 Memory Interface (DDRSS (DDR4 / LPDDR4), MMCSD (eMMC / SD / SDIO), OSPI / QSPI and GPMC)
      1. 7.2.1 DDR Subsystem (DDRSS)
        1. 7.2.1.1 DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
        2. 7.2.1.2 LPDDR4 SDRAM (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.2.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
            1. 7.2.1.2.1.1 Memory Interface Configuration
            2. 7.2.1.2.1.2 Routing Topology and Terminations
            3. 7.2.1.2.1.3 Resistors for Control and Calibration
            4. 7.2.1.2.1.4 Capacitors for the Power Supply Rails
            5. 7.2.1.2.1.5 Data Bit or Byte Swapping
            6. 7.2.1.2.1.6 LPDDR4 Implementation Checklist
      2. 7.2.2 Multi-Media Card/Secure Digital (MMCSD)
        1. 7.2.2.1 MMC0 - eMMC (Embedded Multi-Media Card) Interface
          1. 7.2.2.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
            1. 7.2.2.1.1.1 IO Power Supply
            2. 7.2.2.1.1.2 eMMC (Attached Device) Reset
            3. 7.2.2.1.1.3 Signals Connection
            4. 7.2.2.1.1.4 Capacitors for the Power Supply Rails
            5. 7.2.2.1.1.5 MMC0 (eMMC) Checklist
          2. 7.2.2.1.2 Additional Information on eMMC PHY
          3. 7.2.2.1.3 MMC0 – SD (Secure Digital) Card Interface
        2. 7.2.2.2 MMC1/MMC2 – SD (Secure Digital) Card Interface
          1. 7.2.2.2.1 IO Power Supply
          2. 7.2.2.2.2 SD Card Supply Reset and Boot Configuration
          3. 7.2.2.2.3 Signals Connection
          4. 7.2.2.2.4 ESD Protection
          5. 7.2.2.2.5 Capacitors for the Power Supply Rails
          6. 7.2.2.2.6 MMC1 SD Card Interface Checklist
        3. 7.2.2.3 MMC1 / MMC2 SDIO (Embedded) Interface
          1. 7.2.2.3.1 IO Power Supply
          2. 7.2.2.3.2 Signals Connection
          3. 7.2.2.3.3 MMC2 SDIO (Embedded) Interface Checklist
        4. 7.2.2.4 Additional Information
      3. 7.2.3 Octal Serial Peripheral Interface (OSPI) and Quad Serial Peripheral Interface (QSPI)
        1. 7.2.3.1 IO Power Supply
        2. 7.2.3.2 OSPI / QSPI Reset
        3. 7.2.3.3 Signals Connection
        4. 7.2.3.4 Loopback Clock
        5. 7.2.3.5 Interface to Multiple Devices
        6. 7.2.3.6 Capacitors for the Power Supply Rails
        7. 7.2.3.7 OSPI / QSPI Implementation Checklist
      4. 7.2.4 General-Purpose Memory Controller (GPMC)
        1. 7.2.4.1 IO Power Supply
        2. 7.2.4.2 GPMC Interface
        3. 7.2.4.3 Memory (Attached Device) Reset
        4. 7.2.4.4 Signals Connection
          1. 7.2.4.4.1 GPMC NAND
        5. 7.2.4.5 Capacitors for the Power Supply Rails
        6. 7.2.4.6 GPMC Interface Checklist
    3. 7.3 External Communication Interface (Ethernet (CPSW3G), USB2.0, UART and Controller Area Network (CAN))
      1. 7.3.1 Ethernet Interface Using CPSW3G (Common Platform Ethernet Switch 3-Port Gigabit)
        1. 7.3.1.1  IO Power Supply
        2. 7.3.1.2  Ethernet PHY Reset
        3. 7.3.1.3  Ethernet PHY Pin Strapping
        4. 7.3.1.4  Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
          1. 7.3.1.4.1 Crystal
          2. 7.3.1.4.2 Oscillator
          3. 7.3.1.4.3 Processor Clock Output (CLKOUT0)
        5. 7.3.1.5  MAC (Data, Control and Clock) Interface Signals Connection
        6. 7.3.1.6  External Interrupt (EXTINTn)
          1. 7.3.1.6.1 External Interrupt (EXTINTn) Checklist
        7. 7.3.1.7  MAC (Media Access Controller) to MAC Interface
        8. 7.3.1.8  MDIO (Management Data Input/Output) Interface
        9. 7.3.1.9  Ethernet MDI (Medium Dependent Interface) Including Magnetics
        10. 7.3.1.10 Capacitors for the Power Supply Rails
        11. 7.3.1.11 Ethernet Interface Checklist
      2. 7.3.2 Universal Serial Bus (USB2.0)
        1. 7.3.2.1 USBn (n = 0-1) Used
          1. 7.3.2.1.1 USB Host Interface
          2. 7.3.2.1.2 USB Device Interface
          3. 7.3.2.1.3 USB Dual-Role-Device Interface
          4. 7.3.2.1.4 USB Type-C®
        2. 7.3.2.2 USBn (n = 0-1) Not Used
        3. 7.3.2.3 Additional Information
        4. 7.3.2.4 USB Interface Checklist
      3. 7.3.3 Universal Asynchronous Receiver/Transmitter (UART)
        1. 7.3.3.1 Universal Asynchronous Receiver/Transmitter (UART) Checklist
      4. 7.3.4 Controller Area Network (CAN)
        1. 7.3.4.1 Controller Area Network Checklist
    4. 7.4 On-board Synchronous Communication Interface (MCSPI, MCASP and I2C)
      1. 7.4.1 Multichannel Serial Peripheral Interface (MCSPI) and Multichannel Audio Serial Ports (MCASP)
        1. 7.4.1.1 MCSPI Checklist
        2. 7.4.1.2 MCASP Checklist
      2. 7.4.2 Inter-Integrated Circuit (I2C)
        1. 7.4.2.1 I2C Open-drain Output Type Buffer Checklist
        2. 7.4.2.2 I2C Emulated Open-drain Output Type Buffer Checklist
    5. 7.5 User Interface (CSIRX0, DPI), GPIO and Hardware Diagnostics
      1. 7.5.1 Camera Serial Interface (CSI-Rx (CSI-2 port, CSIRX0 Instance))
        1. 7.5.1.1 CSIRX0 Used
        2. 7.5.1.2 CSIRX0 Not Used
        3. 7.5.1.3 CSI Checklist
      2. 7.5.2 Display Subsystem
        1. 7.5.2.1 Display Parallel Interface (DPI)
          1. 7.5.2.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
            1. 7.5.2.1.1.1 IO Power Supply
            2. 7.5.2.1.1.2 DPI (Attached Device) Reset
            3. 7.5.2.1.1.3 Connection
            4. 7.5.2.1.1.4 Signals Connection
            5. 7.5.2.1.1.5 Capacitors for the Power Supply Rails
            6. 7.5.2.1.1.6 DPI Checklist
      3. 7.5.3 General Purpose Input/Output (GPIO)
        1. 7.5.3.1 Availability of CLKOUT on Processor GPIO
        2. 7.5.3.2 Connection and External Buffering
        3. 7.5.3.3 Additional Information
        4. 7.5.3.4 GPIO Checklist
      4. 7.5.4 On-board Hardware Diagnostics
        1. 7.5.4.1 Monitoring of On-board Supply Voltages Using Processor Voltage Monitors
          1. 7.5.4.1.1 Voltage Monitor Pins Used
            1. 7.5.4.1.1.1 Voltage Monitor Checklist
          2. 7.5.4.1.2 Voltage Monitor Pins Not Used
        2. 7.5.4.2 Internal Temperature Monitoring
          1. 7.5.4.2.1 Internal Temperature Monitoring Checklist
        3. 7.5.4.3 Connection of Error Signal Output (MCU_ERRORn)
        4. 7.5.4.4 High Frequency Oscillator (MCU_OSC0) Clock Loss Detection
    6. 7.6 Verifying Board Level Design Issues
      1. 7.6.1 Processor Pin Configuration Using PinMux Tool
      2. 7.6.2 Schematics Configurations
      3. 7.6.3 Connecting Supply Rails to Pullups
      4. 7.6.4 Peripheral (Subsystem) Clock Outputs
      5. 7.6.5 General Board Bring-up and Debug
        1. 7.6.5.1 Clock Output for Board Bring-Up, Test, or Debug
        2. 7.6.5.2 Additional Information
        3. 7.6.5.3 General Board Bring-up and Debug Checklist
  11. 8 Layout Notes (Added on the Schematic)
    1. 8.1 Layout Checklist
  12. 9 Custom Board Design Simulation
  13. 10Additional References
    1. 10.1 FAQ Covering AM6xx Processor Family
    2. 10.2 FAQs - Processor Product Family Wise and Sitara Processor Families
    3. 10.3 Processor Attached Devices
  14. 11Summary
  15. 12References
    1. 12.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
    2. 12.2 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
    3. 12.3 AM62P / AM62P-Q1
    4. 12.4 Common for all Processor Families
    5. 12.5 Master List of Available FAQs - Processor Family Wise
    6. 12.6 Master List of Available FAQs - Sitara Processor Families
    7. 12.7 FAQs Including Software Related
    8. 12.8 FAQs for Attached Devices
  16. 13Terminology
7.2.2.1.1.5 MMC0 (eMMC) Checklist

General

Review and verify the following for the custom schematic design:

  1. Above sections, including relevant application notes and FAQ links.
  2. Pin attributes, signal description, and electrical specifications.
  3. Electrical characteristics, timing parameters, and any additional available information.
  4. MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51)
  5. AM62Ax processor family implements a soft PHY. The pulls required for DAT0, clock, and control signals are recommended to be implemented externally.
  6. Include a series resistor (0Ω) on MMC0_CLK placed as close to processor clock output pin as possible to dampen reflections. MMC0_CLK is looped back internally on read transactions, and the resistor eliminates possible signal reflections, which cause false clock transitions. Use 0Ω initially and adjust as required to match the PCB trace impedance.
  7. Add pullups (10kΩ or 47kΩ) for DAT0 and CMD signals. Connect the pullup to the IO supply group VDDSHV4 (MMC IO rail). For DAT1-7 eMMC device is expected to have the pullups enabled during reset. The eMMC host/PHY disables the eMMC device pullups and enables processor internal pullups. Provision for external pullups is optional, or delete the pullups.
  8. VDDSHV4 (1.8V or 3.3V) and the attached eMMC device IO supply is required to be powered from the same power source.
  9. Add a pulldown (10kΩ) to the eMMC attached device clock input near to the attached device.
  10. For implementing eMMC device reset, use a 2-input ANDing logic when the memory is used for boot. Connect RESETSTATz as one of the inputs and processor IO as another input. Add a pullup for the processor IO input near the AND gate input pin and an isolation resistor near to the processor IO output. Alternatively, RESETSTATz is used as the reset source. When RESETSTATz is used as the reset source, verify the voltage level compatibility with the eMMC IO supply. Use a level shifter as required.
  11. When eMMC boot is not required, the eMMC attached device reset can be controlled by the processor IO. The recommendation is to pulldown the reset of the eMMC memory device during board power reset.
  12. Add additional decoupling capacitors for attached memory device as required. Refer SK-AM62P-LP schematics.

Schematic Review

Follow the below list for the custom schematic design:

  1. Required bulk and decoupling capacitors are provided for processor and attached device rails. Compare with the SK schematics
  2. Pull values for the data, command, and clock signals. Compare with the relevant SK
  3. Series resistor value and placement on the clock output signal near to the processor clock output
  4. Implementation of reset logic including the IO level compatibility. Adding a capacitor at the reset input of eMMC attached device is not recommended when RESETSTATz or processor IO is connected directly to control the reset. A stand-alone reset connection to reset the eMMC memory device is not recommended
  5. Supply rails connected follow the ROC

Additional

  1. Connect an external pulldown on CLK, and external pullups on CMD and DAT0 to prevent the eMMC device inputs from floating until software initializes the host controller and processor IOs associated with MMC0. The eMMC standard mandates that eMMC devices have internal pullups enabled during reset on DAT1-7, external pullups are not required for DAT1-7 signals. Software turns on the respective internal DAT pullups when the bus width is increased from 1-bit mode to 4-bit or 8-bit mode. External pulls are required because the IOs associated with MMC0 are implemented with standard dual-voltage LVCMOS IO cells with the capability of multiplexing additional signal functions to the respective device pins. MMC0 IOs buffers are off during reset as what interface is connected to MMC0 pins is unknown.
  2. Verify eMMC_RSTn reset input is enabled in the eMMC device (eMMC non-volatile configuration space) for the reset logic to be functional. Software can reset the attached device (eMMC, OSPI, SD card or EPHY) without resetting the entire processor using the GPIO reset option, allowing for a peripheral-specific reset in cases where the peripheral becomes unresponsive. Eliminate the GPIO option and use the reset output, either warm or cold. Software forces a warm reset if the peripheral becomes unresponsive. However, using warm reset resets the entire device, rather than trying to recover the specific peripheral without resetting the entire device. When RESETSTATz is used to reset the attached device, verify the IO voltage level of the attached device matches the RESETSTATz IO voltage level. A level translator is recommended to match the IO voltage level. Alternatively, use a resistor divider and select an optimum impedance value. A slow rise or fall time of the eMMC reset input causes too much delay. Low reset input causes the processor to source too much steady-state current during normal operation.
  3. ANDing logic additionally performs level translation. Verify the reset IO level compatibility before optimizing the reset ANDing logic. IO level mismatch can cause supply leakage and affect processor operation
  4. Pulldown is selected for eMMC, SD card, or other peripherals as there are cases where the clock is stopped or paused in a low logic state and the pulldown option is consistent with the logic state.