SPRS881K August 2014 – February 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S
PRODUCTION DATA
MIN(1) | MAX | UNIT | ||
---|---|---|---|---|
Mode 0 | ||||
tc(SDC)M0 | Cycle time, SDx_Cy | 10 * SYSCLK period | 256 * SYSCLK period | ns |
tw(SDCHL)M0 | Pulse duration, SDx_Cy high/low | 4 * SYSCLK period | 6 * SYSCLK period | ns |
tw(SDDHL)M0 | Pulse duration, SDx_Dy high/low | 4 * SYSCLK period | ns | |
tsu(SDDV-SDCH)M0 | Setup time, SDx_Dy valid before SDx_Cy goes high | 2 * SYSCLK period | ns | |
th(SDCH-SDD)M0 | Hold time, SDx_Dy wait after SDx_Cy goes high | 2 * SYSCLK period | ns | |
Mode 1 | ||||
tc(SDC)M1 | Cycle time, SDx_Cy | 20 * SYSCLK period | 256 * SYSCLK period | ns |
tw(SDCH)M1 | Pulse duration, SDx_Cy high | 4 * SYSCLK period | 6 * SYSCLK period | ns |
tw(SDDHL)M1 | Pulse duration, SDx_Dy high/low | 4 * SYSCLK period | ns | |
tsu(SDDV-SDCL)M1 | Setup time, SDx_Dy valid before SDx_Cy goes low | 2 * SYSCLK period | ns | |
tsu(SDDV-SDCH)M1 | Setup time, SDx_Dy valid before SDx_Cy goes high | 2 * SYSCLK period | ns | |
th(SDCL-SDD)M1 | Hold time, SDx_Dy wait after SDx_Cy goes low | 2 * SYSCLK period | ns | |
th(SDCH-SDD)M1 | Hold time, SDx_Dy wait after SDx_Cy goes high | 2 * SYSCLK period | ns | |
Mode 2 | ||||
tc(SDD)M2 | Cycle time, SDx_Dy | Option unavailable | ||
tw(SDDH)M2 | Pulse duration, SDx_Dy high | |||
Mode 3 | ||||
tc(SDC)M3 | Cycle time, SDx_Cy | 10 * SYSCLK period | 256 * SYSCLK period | ns |
tw(SDCHL)M3 | Pulse duration, SDx_Cy high | 4 * SYSCLK period | 6 * SYSCLK period | ns |
tw(SDDHL)M3 | Pulse duration, SDx_Dy high/low | 4 * SYSCLK period | ns | |
tsu(SDDV-SDCH)M3 | Setup time, SDx_Dy valid before SDx_Cy goes high | 2 * SYSCLK period | ns | |
th(SDCH-SDD)M3 | Hold time, SDx_Dy wait after SDx_Cy goes high | 2 * SYSCLK period | ns |
The SDFM Qualified GPIO (3-sample) mode provides protection against SDFM module corruption due to occasional random noise glitches on the SDx_Cy pin that may result in a false comparator trip and filter output. For more details, refer to the "SDFM: Use Caution While Using SDFM Under Noisy Conditions" usage note in the TMS320F2837xS Real-Time MCUs Silicon Errata.
The SDFM Qualified GPIO (3-sample) mode does not provide protection against persistent violations of the above timing requirements. Timing violations will result in data corruption proportional to the number of bits which violate the requirements.