SPRS902K October 2014 – February 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
PRODUCTION DATA
IDLE, STANDBY, and HALT modes on this device are similar to those on other C28x devices. Table 6-7 describes the effect on the system when any of the clock-gating low-power modes are entered.
MODULES/ CLOCK DOMAIN | CPU1 IDLE | CPU1 STANDBY | HALT |
---|---|---|---|
CPU1.CLKIN | Active | Gated | Gated |
CPU1.SYSCLK | Active | Gated | Gated |
CPU1.CPUCLK | Gated | Gated | Gated |
Clock to modules Connected to PERx.SYSCLK | Active | Gated | Gated |
CPU1.WDCLK | Active | Active | Gated if CLKSRCCTL1.WDHALTI = 0 |
AUXPLLCLK | Active | Active | Gated |
PLL | Powered | Powered | Software must power down PLL before entering HALT |
INTOSC1 | Powered | Powered | Powered down if CLKSRCCTL1.WDHALTI = 0 |
INTOSC2 | Powered | Powered | Powered down if CLKSRCCTL1.WDHALTI = 0 |
Flash | Powered | Powered | Software-Controlled |
X1/X2 Crystal Oscillator | Powered | Powered | Powered-Down |