SPRS945G January   2017  – January 2023 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pin Multiplexing
      1. 6.4.1 GPIO Muxed Pins
      2. 6.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 6.4.3 GPIO Input X-BAR
      4. 6.4.4 GPIO Output X-BAR and ePWM X-BAR
    5. 6.5 Pins With Internal Pullup and Pulldown
    6. 6.6 Connections for Unused Pins
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption (External Supply)
      2. 7.5.2 System Current Consumption (Internal VREG)
      3. 7.5.3 System Current Consumption (DCDC)
      4. 7.5.4 Operating Mode Test Description
      5. 7.5.5 Current Consumption Graphs
      6. 7.5.6 Reducing Current Consumption
        1. 7.5.6.1 Typical IDD Current Reduction per Disabled Peripheral (at 100-MHz SYSCLK)
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics
      1. 7.7.1 PZ Package
      2. 7.7.2 PM Package
      3. 7.7.3 RSH Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  System
      1. 7.9.1 Power Management Module (PMM)
        1. 7.9.1.1 Introduction
        2. 7.9.1.2 Overview
          1. 7.9.1.2.1 Power Rail Monitors
            1. 7.9.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 7.9.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 7.9.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 7.9.1.2.2 External Supervisor Usage
          3. 7.9.1.2.3 Delay Blocks
          4. 7.9.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 7.9.1.2.5 VREGENZ
          6. 7.9.1.2.6 Internal 1.2-V Switching Regulator (DC-DC)
            1. 7.9.1.2.6.1 PCB Layout and Component Guidelines
        3. 7.9.1.3 External Components
          1. 7.9.1.3.1 Decoupling Capacitors
            1. 7.9.1.3.1.1 VDDIO Decoupling
            2. 7.9.1.3.1.2 VDD Decoupling
        4. 7.9.1.4 Power Sequencing
          1. 7.9.1.4.1 Supply Pins Ganging
          2. 7.9.1.4.2 Signal Pins Power Sequence
          3. 7.9.1.4.3 Supply Pins Power Sequence
            1. 7.9.1.4.3.1 External VREG/VDD Mode Sequence
            2. 7.9.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 7.9.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 7.9.1.4.3.4 Supply Slew Rate
        5. 7.9.1.5 Power Management Module Electrical Data and Timing
          1. 7.9.1.5.1 Power Management Module Operating Conditions
          2. 7.9.1.5.2 Power Management Module Characteristics
          3.        Supply Voltages
      2. 7.9.2 Reset Timing
        1. 7.9.2.1 Reset Sources
        2. 7.9.2.2 Reset Electrical Data and Timing
          1. 7.9.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.9.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.9.2.2.3 Reset Timing Diagram
      3. 7.9.3 Clock Specifications
        1. 7.9.3.1 Clock Sources
        2. 7.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.9.3.2.1.1 Input Clock Frequency
            2. 7.9.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.9.3.2.1.3 X1 Timing Requirements
            4. 7.9.3.2.1.4 PLL Lock Times
          2. 7.9.3.2.2 Internal Clock Frequencies
            1. 7.9.3.2.2.1 Internal Clock Frequencies
          3. 7.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 7.9.3.2.3.1 XCLKOUT Switching Characteristics
        3. 7.9.3.3 Input Clocks and PLLs
        4. 7.9.3.4 Crystal (XTAL) Oscillator
          1. 7.9.3.4.1 Introduction
          2. 7.9.3.4.2 Overview
            1. 7.9.3.4.2.1 Electrical Oscillator
              1. 7.9.3.4.2.1.1 Modes of Operation
                1. 7.9.3.4.2.1.1.1 Crystal Mode of Operation
                2. 7.9.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 7.9.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 7.9.3.4.2.2 Quartz Crystal
            3. 7.9.3.4.2.3 GPIO Modes of Operation
          3. 7.9.3.4.3 Functional Operation
            1. 7.9.3.4.3.1 ESR – Effective Series Resistance
            2. 7.9.3.4.3.2 Rneg – Negative Resistance
            3. 7.9.3.4.3.3 Start-up Time
            4. 7.9.3.4.3.4 DL – Drive Level
          4. 7.9.3.4.4 How to Choose a Crystal
          5. 7.9.3.4.5 Testing
          6. 7.9.3.4.6 Common Problems and Debug Tips
          7. 7.9.3.4.7 Crystal Oscillator Specifications
            1. 7.9.3.4.7.1 Crystal Oscillator Parameters
            2. 7.9.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 7.9.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 7.9.3.5 Internal Oscillators
          1. 7.9.3.5.1 INTOSC Characteristics
      4. 7.9.4 Flash Parameters
      5. 7.9.5 Emulation/JTAG
        1. 7.9.5.1 JTAG Electrical Data and Timing
          1. 7.9.5.1.1 JTAG Timing Requirements
          2. 7.9.5.1.2 JTAG Switching Characteristics
          3. 7.9.5.1.3 JTAG Timing Diagram
        2. 7.9.5.2 cJTAG Electrical Data and Timing
          1. 7.9.5.2.1 cJTAG Timing Requirements
          2. 7.9.5.2.2 cJTAG Switching Characteristics
          3. 7.9.5.2.3 cJTAG Timing Diagram
      6. 7.9.6 GPIO Electrical Data and Timing
        1. 7.9.6.1 GPIO – Output Timing
          1. 7.9.6.1.1 General-Purpose Output Switching Characteristics
        2. 7.9.6.2 GPIO – Input Timing
          1. 7.9.6.2.1 General-Purpose Input Timing Requirements
        3. 7.9.6.3 Sampling Window Width for Input Signals
      7. 7.9.7 Interrupts
        1. 7.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.9.7.1.1 External Interrupt Timing Requirements
          2. 7.9.7.1.2 External Interrupt Switching Characteristics
          3. 7.9.7.1.3 Interrupt Timing Diagram
      8. 7.9.8 Low-Power Modes
        1. 7.9.8.1 Clock-Gating Low-Power Modes
        2. 7.9.8.2 Low-Power Mode Wake-up Timing
          1. 7.9.8.2.1 IDLE Mode Timing Requirements
          2. 7.9.8.2.2 IDLE Mode Switching Characteristics
          3. 7.9.8.2.3 IDLE Mode Timing Diagram
          4. 7.9.8.2.4 HALT Mode Timing Requirements
          5. 7.9.8.2.5 HALT Mode Switching Characteristics
          6. 7.9.8.2.6 HALT Mode Timing Diagram
    10. 7.10 Analog Peripherals
      1. 7.10.1 Analog-to-Digital Converter (ADC)
        1. 7.10.1.1 Result Register Mapping
        2. 7.10.1.2 ADC Configurability
          1. 7.10.1.2.1 Signal Mode
        3. 7.10.1.3 ADC Electrical Data and Timing
          1. 7.10.1.3.1 ADC Operating Conditions
          2. 7.10.1.3.2 ADC Characteristics
          3. 7.10.1.3.3 ADC Input Model
          4. 7.10.1.3.4 ADC Timing Diagrams
      2. 7.10.2 Programmable Gain Amplifier (PGA)
        1. 7.10.2.1 PGA Electrical Data and Timing
          1. 7.10.2.1.1 PGA Operating Conditions
          2. 7.10.2.1.2 PGA Characteristics
          3. 7.10.2.1.3 PGA Typical Characteristics Graphs
      3. 7.10.3 Temperature Sensor
        1. 7.10.3.1 Temperature Sensor Electrical Data and Timing
          1. 7.10.3.1.1 Temperature Sensor Characteristics
      4. 7.10.4 Buffered Digital-to-Analog Converter (DAC)
        1. 7.10.4.1 Buffered DAC Electrical Data and Timing
          1. 7.10.4.1.1 Buffered DAC Operating Conditions
          2. 7.10.4.1.2 Buffered DAC Electrical Characteristics
          3. 7.10.4.1.3 Buffered DAC Illustrative Graphs
          4. 7.10.4.1.4 Buffered DAC Typical Characteristics Graphs
      5. 7.10.5 Comparator Subsystem (CMPSS)
        1. 7.10.5.1 CMPSS Electrical Data and Timing
          1. 7.10.5.1.1 Comparator Electrical Characteristics
          2. 7.10.5.1.2 CMPSS DAC Static Electrical Characteristics
          3. 7.10.5.1.3 CMPSS Illustrative Graphs
    11. 7.11 Control Peripherals
      1. 7.11.1 Enhanced Capture (eCAP)
        1. 7.11.1.1 eCAP Electrical Data and Timing
          1. 7.11.1.1.1 eCAP Timing Requirements
          2. 7.11.1.1.2 eCAP Switching Characteristics
      2. 7.11.2 High-Resolution Capture Submodule (HRCAP6–HRCAP7)
        1. 7.11.2.1 HRCAP Electrical Data and Timing
          1. 7.11.2.1.1 HRCAP Switching Characteristics
      3. 7.11.3 Enhanced Pulse Width Modulator (ePWM)
        1. 7.11.3.1 Control Peripherals Synchronization
        2. 7.11.3.2 ePWM Electrical Data and Timing
          1. 7.11.3.2.1 ePWM Timing Requirements
          2. 7.11.3.2.2 ePWM Switching Characteristics
          3. 7.11.3.2.3 Trip-Zone Input Timing
            1. 7.11.3.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.11.3.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.11.3.3.1 External ADC Start-of-Conversion Switching Characteristics
      4. 7.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.11.4.1 HRPWM Electrical Data and Timing
          1. 7.11.4.1.1 High-Resolution PWM Characteristics
      5. 7.11.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.11.5.1 eQEP Electrical Data and Timing
          1. 7.11.5.1.1 eQEP Timing Requirements
          2. 7.11.5.1.2 eQEP Switching Characteristics
      6. 7.11.6 Sigma-Delta Filter Module (SDFM)
        1. 7.11.6.1 SDFM Electrical Data and Timing
          1. 7.11.6.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
          2. 7.11.6.1.2 SDFM Timing Diagram
        2. 7.11.6.2 SDFM Electrical Data and Timing (Synchronized GPIO)
          1. 7.11.6.2.1 SDFM Timing Requirements When Using Synchronized GPIO (SYNC) Option
    12. 7.12 Communications Peripherals
      1. 7.12.1 Controller Area Network (CAN)
      2. 7.12.2 Inter-Integrated Circuit (I2C)
        1. 7.12.2.1 I2C Electrical Data and Timing
          1. 7.12.2.1.1 I2C Timing Requirements
          2. 7.12.2.1.2 I2C Switching Characteristics
          3. 7.12.2.1.3 I2C Timing Diagram
      3. 7.12.3 Power Management Bus (PMBus) Interface
        1. 7.12.3.1 PMBus Electrical Data and Timing
          1. 7.12.3.1.1 PMBus Electrical Characteristics
          2. 7.12.3.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.12.3.1.3 PMBus Standard Mode Switching Characteristics
      4. 7.12.4 Serial Communications Interface (SCI)
      5. 7.12.5 Serial Peripheral Interface (SPI)
        1. 7.12.5.1 SPI Electrical Data and Timing
          1. 7.12.5.1.1 Non-High-Speed Master Mode Timings
            1. 7.12.5.1.1.1 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            2. 7.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            3. 7.12.5.1.1.3 SPI Master Mode Timing Requirements
          2. 7.12.5.1.2 Non-High-Speed Slave Mode Timings
            1. 7.12.5.1.2.1 SPI Slave Mode Switching Characteristics
            2. 7.12.5.1.2.2 SPI Slave Mode Timing Requirements
          3. 7.12.5.1.3 High-Speed Master Mode Timings
            1. 7.12.5.1.3.1 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
            2. 7.12.5.1.3.2 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
            3. 7.12.5.1.3.3 SPI High-Speed Master Mode Timing Requirements
          4. 7.12.5.1.4 High-Speed Slave Mode Timings
            1. 7.12.5.1.4.1 SPI High-Speed Slave Mode Switching Characteristics
            2. 7.12.5.1.4.2 SPI High-Speed Slave Mode Timing Requirements
      6. 7.12.6 Local Interconnect Network (LIN)
      7. 7.12.7 Fast Serial Interface (FSI)
        1. 7.12.7.1 FSI Transmitter
          1. 7.12.7.1.1 FSITX Electrical Data and Timing
            1. 7.12.7.1.1.1 FSITX Switching Characteristics
        2. 7.12.7.2 FSI Receiver
          1. 7.12.7.2.1 FSIRX Electrical Data and Timing
            1. 7.12.7.2.1.1 FSIRX Switching Characteristics
            2. 7.12.7.2.1.2 FSIRX Timing Requirements
        3. 7.12.7.3 FSI SPI Compatibility Mode
          1. 7.12.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.12.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Memory
      1. 8.3.1 C28x Memory Map
      2. 8.3.2 Control Law Accelerator (CLA) ROM Memory Map
      3. 8.3.3 Flash Memory Map
      4. 8.3.4 Peripheral Registers Memory Map
      5. 8.3.5 Memory Types
        1. 8.3.5.1 Dedicated RAM (Mx RAM)
        2. 8.3.5.2 Local Shared RAM (LSx RAM)
        3. 8.3.5.3 Global Shared RAM (GSx RAM)
        4. 8.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 8.4  Identification
    5. 8.5  Bus Architecture – Peripheral Connectivity
    6. 8.6  C28x Processor
      1. 8.6.1 Embedded Real-Time Analysis and Diagnostic (ERAD)
      2. 8.6.2 Floating-Point Unit (FPU)
      3. 8.6.3 Trigonometric Math Unit (TMU)
      4. 8.6.4 Viterbi, Complex Math and CRC Unit (VCU-I)
    7. 8.7  Control Law Accelerator (CLA)
    8. 8.8  Direct Memory Access (DMA)
    9. 8.9  Boot ROM and Peripheral Booting
      1. 8.9.1 Configuring Alternate Boot Mode Select Pins
      2. 8.9.2 Configuring Alternate Boot Mode Options
      3. 8.9.3 GPIO Assignments
    10. 8.10 Dual Code Security Module
    11. 8.11 Watchdog
    12. 8.12 Configurable Logic Block (CLB)
    13. 8.13 Functional Safety
  9. 9 Applications, Implementation, and Layout
    1. 9.1 Key Device Features
    2. 9.2 Application Information
      1. 9.2.1 Typical Application
        1. 9.2.1.1 Server Telecom Power Supply Unit (PSU)
          1. 9.2.1.1.1 System Block Diagram
          2. 9.2.1.1.2 Server and Telecom PSU Resources
        2. 9.2.1.2 Single-Phase Online UPS
          1. 9.2.1.2.1 System Block Diagram
          2. 9.2.1.2.2 Single phase online UPS Resources
        3. 9.2.1.3 Solar Micro Inverter
          1. 9.2.1.3.1 System Block Diagram
          2. 9.2.1.3.2 Solar Micro Inverter Resources
        4. 9.2.1.4 EV Charging Station Power Module
          1. 9.2.1.4.1 System Block Diagram
          2. 9.2.1.4.2 EV charging station power module Resources
        5. 9.2.1.5 Servo Drive Control Module
          1. 9.2.1.5.1 System Block Diagram
          2. 9.2.1.5.2 Servo Drive Control Module Resources
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Markings
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

6.3.2 Digital Signals

Table 6-3 Digital Signals
SIGNAL NAMEDESCRIPTIONPIN TYPEGPIO100 PZ64 PMQ64 PM56 RSH
ADCSOCAOADC Start of Conversion A Output for External ADC (from ePWM modules)O874474742
ADCSOCBOADC Start of Conversion B Output for External ADC (from ePWM modules)O10936363
CANA_RXCAN-A ReceiveI18, 30, 33, 35, 553, 63, 68, 89, 9832, 39, 41, 6132, 39, 41, 6129, 36, 38, 55
CANA_TXCAN-A TransmitO31, 32, 37, 461, 64, 75, 9937, 40, 4837, 40, 4834, 37, 43
CANB_RXCAN-B ReceiveI10, 13, 17, 39, 59, 750, 55, 84, 91, 92, 9334, 57, 6329, 34, 57, 6326, 31, 52
CANB_TXCAN-B TransmitO12, 16, 58, 6, 851, 54, 67, 74, 9733, 47, 6430, 33, 47, 641, 27, 30, 42
EPWM1_AePWM-1 Output AO079525247
EPWM1_BePWM-1 Output BO178515146
EPWM2_AePWM-2 Output AO277505045
EPWM2_BePWM-2 Output BO376494944
EPWM3_AePWM-3 Output AO475484843
EPWM3_BePWM-3 Output BO589616155
EPWM4_AePWM-4 Output AO69764641
EPWM4_BePWM-4 Output BO784575752
EPWM5_AePWM-5 Output AO16, 854, 7433, 4733, 4730, 42
EPWM5_BePWM-5 Output BO17, 955, 9034, 6234, 6231, 56
EPWM6_AePWM-6 Output AO10, 1868, 9341, 6341, 6338
EPWM6_BePWM-6 Output BO1152313128
EPWM7_AePWM-7 Output AO12, 281, 5122, 3027, 3
EPWM7_BePWM-7 Output BO13, 29100, 5011, 292, 26
EPWM8_AePWM-8 Output AO14, 2456, 96353532
EPWM8_BePWM-8 Output BO15, 3264, 95404037
EQEP1_AeQEP-1 Input AI10, 28, 35, 40, 56, 61, 63, 65, 85, 93, 972, 39, 63, 642, 39, 63, 641, 3, 36
EQEP1_BeQEP-1 Input BI11, 29, 37, 57, 7100, 52, 61, 66, 841, 31, 37, 571, 31, 37, 572, 28, 34, 52
EQEP1_INDEXeQEP-1 IndexI/O13, 17, 31, 59, 950, 55, 90, 92, 9934, 6229, 34, 6226, 31, 56
EQEP1_STROBEeQEP-1 StrobeI/O12, 16, 22, 30, 58, 851, 54, 67, 74, 83, 9833, 47, 5630, 33, 47, 5627, 30, 42, 51
EQEP2_AeQEP-2 Input AI14, 18, 2456, 68, 9635, 4135, 4132, 38
EQEP2_BeQEP-2 Input BI15, 2557, 95
EQEP2_INDEXeQEP-2 IndexI/O26, 29, 57100, 58, 66112
EQEP2_STROBEeQEP-2 StrobeI/O27, 28, 561, 59, 65223
ERRORSTSActive-low Error Status Output. If you want an error state to be asserted during power up or during a fault with the ERRORSTS signal itself, an external pulldown resistor may be used. A pullup resistor may be used if you do not want an error state asserted for the conditions mentioned. O24, 28, 291, 100, 561, 2, 351, 2, 352, 3, 32
FSIRXA_CLKFSIRX-A Input ClockI13, 33, 39, 450, 53, 75, 9132, 4829, 32, 4826, 29, 43
FSIRXA_D0FSIRX-A Primary Data InputI12, 3, 32, 4051, 64, 76, 8540, 4930, 40, 4927, 37, 44
FSIRXA_D1FSIRX-A Optional Additional Data InputI11, 2, 3152, 77, 9931, 5031, 5028, 45
FSITXA_CLKFSITX-A Output ClockO10, 27, 759, 84, 9357, 6357, 6352
FSITXA_D0FSITX-A Primary Data OutputO26, 6, 958, 90, 9762, 6462, 641, 56
FSITXA_D1FSITX-A Optional Additional Data OutputO25, 5, 857, 74, 8947, 6147, 6142, 55
GPIO0General-Purpose Input Output 0I/O079525247
GPIO1General-Purpose Input Output 1I/O178515146
GPIO2General-Purpose Input Output 2I/O277505045
GPIO3General-Purpose Input Output 3I/O376494944
GPIO4General-Purpose Input Output 4I/O475484843
GPIO5General-Purpose Input Output 5I/O589616155
GPIO6General-Purpose Input Output 6I/O69764641
GPIO7General-Purpose Input Output 7I/O784575752
GPIO8General-Purpose Input Output 8I/O874474742
GPIO9General-Purpose Input Output 9I/O990626256
GPIO10General-Purpose Input Output 10I/O10936363
GPIO11General-Purpose Input Output 11I/O1152313128
GPIO12General-Purpose Input Output 12I/O12513027
GPIO13General-Purpose Input Output 13I/O13502926
GPIO14General-Purpose Input Output 14I/O1496
GPIO15General-Purpose Input Output 15I/O1595
GPIO16General-Purpose Input Output 16I/O1654333330
GPIO17General-Purpose Input Output 17I/O1755343431
GPIO18_X2General-Purpose Input Output 18. This pin and its digital mux options can only be used when the system is clocked by INTOSC and X1 has an external pulldown resistor (recommended 1 kΩ).I/O1868414138
GPIO20General-Purpose Input Output 20I/O20
GPIO21General-Purpose Input Output 21I/O21
GPIO22_VFBSWGeneral-Purpose Input Output 22. This pin is configured for DC-DC mode by default. If the internal DC-DC regulator is not used, this can be configured as General-Purpose Input Output 22 by disabling DC-DC and clearing their bits in GPAAMSEL register.I/O2283565651
GPIO23_VSWGeneral-Purpose Input Output 23. This pin is configured for DC-DC mode by default. If the internal DC-DC regulator is not used, this can be configured as General-Purpose Input Output 23 by disabling DC-DC and clearing their bits in GPAAMSEL register. This pin has an internal capacitance of approximately 100 pF. TI Recommends using an alternate GPIO, or using this pin only for applications which do not require a fast switching response.I/O2381545449
GPIO24General-Purpose Input Output 24I/O2456353532
GPIO25General-Purpose Input Output 25I/O2557
GPIO26General-Purpose Input Output 26I/O2658
GPIO27General-Purpose Input Output 27I/O2759
GPIO28General-Purpose Input Output 28I/O281223
GPIO29General-Purpose Input Output 29I/O29100112
GPIO30General-Purpose Input Output 30I/O3098
GPIO31General-Purpose Input Output 31I/O3199
GPIO32General-Purpose Input Output 32I/O3264404037
GPIO33General-Purpose Input Output 33I/O3353323229
GPIO34General-Purpose Input Output 34I/O3494
GPIO35General-Purpose Input Output 35I/O3563393936
GPIO37General-Purpose Input Output 37I/O3761373734
GPIO39General-Purpose Input Output 39I/O3991
GPIO40General-Purpose Input Output 40I/O4085
GPIO41General-Purpose Input Output 41I/O41
GPIO42General-Purpose Input Output 42I/O42
GPIO43General-Purpose Input Output 43I/O43
GPIO44General-Purpose Input Output 44I/O44
GPIO45General-Purpose Input Output 45I/O45
GPIO46General-Purpose Input Output 46I/O46
GPIO47General-Purpose Input Output 47I/O47
GPIO48General-Purpose Input Output 48I/O48
GPIO49General-Purpose Input Output 49I/O49
GPIO50General-Purpose Input Output 50I/O50
GPIO51General-Purpose Input Output 51I/O51
GPIO52General-Purpose Input Output 52I/O52
GPIO53General-Purpose Input Output 53I/O53
GPIO54General-Purpose Input Output 54I/O54
GPIO55General-Purpose Input Output 55I/O55
GPIO56General-Purpose Input Output 56I/O5665
GPIO57General-Purpose Input Output 57I/O5766
GPIO58General-Purpose Input Output 58I/O5867
GPIO59General-Purpose Input Output 59I/O5992
I2CA_SCLI2C-A Open-Drain Bidirectional ClockI/OD1, 18, 27, 33, 37, 853, 59, 61, 68, 74, 7832, 37, 41, 47, 5132, 37, 41, 47, 5129, 34, 38, 42, 46
I2CA_SDAI2C-A Open-Drain Bidirectional DataI/OD0, 10, 26, 32, 3558, 63, 64, 79, 9339, 40, 52, 6339, 40, 52, 6336, 37, 47
LINA_RXLIN-A ReceiveI29, 33, 35, 59100, 53, 63, 921, 32, 391, 32, 392, 29, 36
LINA_TXLIN-A TransmitO22, 28, 32, 37, 581, 61, 64, 67, 832, 37, 40, 562, 37, 40, 563, 34, 37, 51
OUTPUTXBAR1Output X-BAR Output 1O2, 24, 34, 5856, 67, 77, 9435, 5035, 5032, 45
OUTPUTXBAR2Output X-BAR Output 2O25, 3, 37, 5957, 61, 76, 9237, 4937, 4934, 44
OUTPUTXBAR3Output X-BAR Output 3O14, 26, 4, 558, 75, 89, 9648, 6148, 6143, 55
OUTPUTXBAR4Output X-BAR Output 4O15, 27, 33, 653, 59, 95, 9732, 6432, 641, 29
OUTPUTXBAR5Output X-BAR Output 5O28, 71, 842, 572, 573, 52
OUTPUTXBAR6Output X-BAR Output 6O29, 9100, 901, 621, 622, 56
OUTPUTXBAR7Output X-BAR Output 7O11, 16, 3052, 54, 9831, 3331, 3328, 30
OUTPUTXBAR8Output X-BAR Output 8O17, 3155, 99343431
PMBUSA_ALERTPMBus-A Open-Drain Bidirectional Alert SignalI/OD13, 27, 3750, 59, 613729, 3726, 34
PMBUSA_CTLPMBus-A Control SignalI12, 18, 26, 3551, 58, 63, 6839, 4130, 39, 4127, 36, 38
PMBUSA_SCLPMBus-A Open-Drain Bidirectional ClockI/OD15, 16, 24, 3, 3554, 56, 63, 76, 9533, 35, 39, 4933, 35, 39, 4930, 32, 36, 44
PMBUSA_SDAPMBus-A Open-Drain Bidirectional DataI/OD14, 17, 2, 25, 34, 4055, 57, 77, 85, 94, 9634, 5034, 5031, 45
SCIA_RXSCI-A Receive DataI17, 25, 28, 3, 35, 91, 55, 57, 63, 76, 902, 34, 39, 49, 622, 34, 39, 49, 623, 31, 36, 44, 56
SCIA_TXSCI-A Transmit DataO16, 2, 24, 29, 37, 8100, 54, 56, 61, 74, 771, 33, 35, 37, 47, 501, 33, 35, 37, 47, 502, 30, 32, 34, 42, 45
SCIB_RXSCI-B Receive DataI11, 13, 15, 5750, 52, 66, 953129, 3126, 28
SCIB_TXSCI-B Transmit DataO10, 12, 14, 18, 22, 40, 56, 951, 65, 68, 83, 85, 90, 93, 9641, 56, 62, 6330, 41, 56, 62, 6327, 38, 51, 56
SD1_C1SDFM-1 Channel 1 Clock InputI17, 2555, 57343431
SD1_C2SDFM-1 Channel 2 Clock InputI2759
SD1_C3SDFM-1 Channel 3 Clock InputI29, 33, 57100, 53, 661, 321, 322, 29
SD1_C4SDFM-1 Channel 4 Clock InputI31, 5992, 99
SD1_D1SDFM-1 Channel 1 Data InputI16, 2454, 5633, 3533, 3530, 32
SD1_D2SDFM-1 Channel 2 Data InputI18, 2658, 68414138
SD1_D3SDFM-1 Channel 3 Data InputI28, 32, 561, 64, 652, 402, 403, 37
SD1_D4SDFM-1 Channel 4 Data InputI22, 30, 5867, 83, 98565651
SPIA_CLKSPI-A ClockI/O18, 3, 56, 965, 68, 76, 9041, 49, 6241, 49, 6238, 44, 56
SPIA_SIMOSPI-A Slave In, Master Out (SIMO)I/O16, 854, 7433, 4733, 4730, 42
SPIA_SOMISPI-A Slave Out, Master In (SOMI)I/O10, 1755, 9334, 6334, 6331
SPIA_STESPI-A Slave Transmit Enable (STE)I/O11, 5, 5752, 66, 8931, 6131, 6128, 55
SPIB_CLKSPI-B ClockI/O14, 22, 26, 28, 32, 581, 58, 64, 67, 83, 962, 40, 562, 40, 563, 37, 51
SPIB_SIMOSPI-B Slave In, Master Out (SIMO)I/O24, 30, 56, 756, 65, 84, 9835, 5735, 5732, 52
SPIB_SOMISPI-B Slave Out, Master In (SOMI)I/O25, 31, 57, 657, 66, 97, 9964641
SPIB_STESPI-B Slave Transmit Enable (STE)I/O15, 27, 29, 33, 59100, 53, 59, 92, 951, 321, 322, 29
SYNCOUTExternal ePWM Synchronization PulseO69764641
TDIJTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input.I3563393936
TDOJTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input.O3761373734
VFBSWInternal DC-DC regulator feedback signal. If the internal DC-DC regulator is used, tie this pin to the node where L(VSW) connects to the VDD rail (as close as possible to the device).-2283565651
VSWSwitching output of the internal DC-DC regulator-2381545449
X2Crystal oscillator outputI/O1868414138
XCLKOUTExternal Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.O16, 1854, 6833, 4133, 4130, 38