SPRS945G January   2017  – January 2023 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pin Multiplexing
      1. 6.4.1 GPIO Muxed Pins
      2. 6.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 6.4.3 GPIO Input X-BAR
      4. 6.4.4 GPIO Output X-BAR and ePWM X-BAR
    5. 6.5 Pins With Internal Pullup and Pulldown
    6. 6.6 Connections for Unused Pins
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption (External Supply)
      2. 7.5.2 System Current Consumption (Internal VREG)
      3. 7.5.3 System Current Consumption (DCDC)
      4. 7.5.4 Operating Mode Test Description
      5. 7.5.5 Current Consumption Graphs
      6. 7.5.6 Reducing Current Consumption
        1. 7.5.6.1 Typical IDD Current Reduction per Disabled Peripheral (at 100-MHz SYSCLK)
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics
      1. 7.7.1 PZ Package
      2. 7.7.2 PM Package
      3. 7.7.3 RSH Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  System
      1. 7.9.1 Power Management Module (PMM)
        1. 7.9.1.1 Introduction
        2. 7.9.1.2 Overview
          1. 7.9.1.2.1 Power Rail Monitors
            1. 7.9.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 7.9.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 7.9.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 7.9.1.2.2 External Supervisor Usage
          3. 7.9.1.2.3 Delay Blocks
          4. 7.9.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 7.9.1.2.5 VREGENZ
          6. 7.9.1.2.6 Internal 1.2-V Switching Regulator (DC-DC)
            1. 7.9.1.2.6.1 PCB Layout and Component Guidelines
        3. 7.9.1.3 External Components
          1. 7.9.1.3.1 Decoupling Capacitors
            1. 7.9.1.3.1.1 VDDIO Decoupling
            2. 7.9.1.3.1.2 VDD Decoupling
        4. 7.9.1.4 Power Sequencing
          1. 7.9.1.4.1 Supply Pins Ganging
          2. 7.9.1.4.2 Signal Pins Power Sequence
          3. 7.9.1.4.3 Supply Pins Power Sequence
            1. 7.9.1.4.3.1 External VREG/VDD Mode Sequence
            2. 7.9.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 7.9.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 7.9.1.4.3.4 Supply Slew Rate
        5. 7.9.1.5 Power Management Module Electrical Data and Timing
          1. 7.9.1.5.1 Power Management Module Operating Conditions
          2. 7.9.1.5.2 Power Management Module Characteristics
          3.        Supply Voltages
      2. 7.9.2 Reset Timing
        1. 7.9.2.1 Reset Sources
        2. 7.9.2.2 Reset Electrical Data and Timing
          1. 7.9.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.9.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.9.2.2.3 Reset Timing Diagram
      3. 7.9.3 Clock Specifications
        1. 7.9.3.1 Clock Sources
        2. 7.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.9.3.2.1.1 Input Clock Frequency
            2. 7.9.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.9.3.2.1.3 X1 Timing Requirements
            4. 7.9.3.2.1.4 PLL Lock Times
          2. 7.9.3.2.2 Internal Clock Frequencies
            1. 7.9.3.2.2.1 Internal Clock Frequencies
          3. 7.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 7.9.3.2.3.1 XCLKOUT Switching Characteristics
        3. 7.9.3.3 Input Clocks and PLLs
        4. 7.9.3.4 Crystal (XTAL) Oscillator
          1. 7.9.3.4.1 Introduction
          2. 7.9.3.4.2 Overview
            1. 7.9.3.4.2.1 Electrical Oscillator
              1. 7.9.3.4.2.1.1 Modes of Operation
                1. 7.9.3.4.2.1.1.1 Crystal Mode of Operation
                2. 7.9.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 7.9.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 7.9.3.4.2.2 Quartz Crystal
            3. 7.9.3.4.2.3 GPIO Modes of Operation
          3. 7.9.3.4.3 Functional Operation
            1. 7.9.3.4.3.1 ESR – Effective Series Resistance
            2. 7.9.3.4.3.2 Rneg – Negative Resistance
            3. 7.9.3.4.3.3 Start-up Time
            4. 7.9.3.4.3.4 DL – Drive Level
          4. 7.9.3.4.4 How to Choose a Crystal
          5. 7.9.3.4.5 Testing
          6. 7.9.3.4.6 Common Problems and Debug Tips
          7. 7.9.3.4.7 Crystal Oscillator Specifications
            1. 7.9.3.4.7.1 Crystal Oscillator Parameters
            2. 7.9.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 7.9.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 7.9.3.5 Internal Oscillators
          1. 7.9.3.5.1 INTOSC Characteristics
      4. 7.9.4 Flash Parameters
      5. 7.9.5 Emulation/JTAG
        1. 7.9.5.1 JTAG Electrical Data and Timing
          1. 7.9.5.1.1 JTAG Timing Requirements
          2. 7.9.5.1.2 JTAG Switching Characteristics
          3. 7.9.5.1.3 JTAG Timing Diagram
        2. 7.9.5.2 cJTAG Electrical Data and Timing
          1. 7.9.5.2.1 cJTAG Timing Requirements
          2. 7.9.5.2.2 cJTAG Switching Characteristics
          3. 7.9.5.2.3 cJTAG Timing Diagram
      6. 7.9.6 GPIO Electrical Data and Timing
        1. 7.9.6.1 GPIO – Output Timing
          1. 7.9.6.1.1 General-Purpose Output Switching Characteristics
        2. 7.9.6.2 GPIO – Input Timing
          1. 7.9.6.2.1 General-Purpose Input Timing Requirements
        3. 7.9.6.3 Sampling Window Width for Input Signals
      7. 7.9.7 Interrupts
        1. 7.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.9.7.1.1 External Interrupt Timing Requirements
          2. 7.9.7.1.2 External Interrupt Switching Characteristics
          3. 7.9.7.1.3 Interrupt Timing Diagram
      8. 7.9.8 Low-Power Modes
        1. 7.9.8.1 Clock-Gating Low-Power Modes
        2. 7.9.8.2 Low-Power Mode Wake-up Timing
          1. 7.9.8.2.1 IDLE Mode Timing Requirements
          2. 7.9.8.2.2 IDLE Mode Switching Characteristics
          3. 7.9.8.2.3 IDLE Mode Timing Diagram
          4. 7.9.8.2.4 HALT Mode Timing Requirements
          5. 7.9.8.2.5 HALT Mode Switching Characteristics
          6. 7.9.8.2.6 HALT Mode Timing Diagram
    10. 7.10 Analog Peripherals
      1. 7.10.1 Analog-to-Digital Converter (ADC)
        1. 7.10.1.1 Result Register Mapping
        2. 7.10.1.2 ADC Configurability
          1. 7.10.1.2.1 Signal Mode
        3. 7.10.1.3 ADC Electrical Data and Timing
          1. 7.10.1.3.1 ADC Operating Conditions
          2. 7.10.1.3.2 ADC Characteristics
          3. 7.10.1.3.3 ADC Input Model
          4. 7.10.1.3.4 ADC Timing Diagrams
      2. 7.10.2 Programmable Gain Amplifier (PGA)
        1. 7.10.2.1 PGA Electrical Data and Timing
          1. 7.10.2.1.1 PGA Operating Conditions
          2. 7.10.2.1.2 PGA Characteristics
          3. 7.10.2.1.3 PGA Typical Characteristics Graphs
      3. 7.10.3 Temperature Sensor
        1. 7.10.3.1 Temperature Sensor Electrical Data and Timing
          1. 7.10.3.1.1 Temperature Sensor Characteristics
      4. 7.10.4 Buffered Digital-to-Analog Converter (DAC)
        1. 7.10.4.1 Buffered DAC Electrical Data and Timing
          1. 7.10.4.1.1 Buffered DAC Operating Conditions
          2. 7.10.4.1.2 Buffered DAC Electrical Characteristics
          3. 7.10.4.1.3 Buffered DAC Illustrative Graphs
          4. 7.10.4.1.4 Buffered DAC Typical Characteristics Graphs
      5. 7.10.5 Comparator Subsystem (CMPSS)
        1. 7.10.5.1 CMPSS Electrical Data and Timing
          1. 7.10.5.1.1 Comparator Electrical Characteristics
          2. 7.10.5.1.2 CMPSS DAC Static Electrical Characteristics
          3. 7.10.5.1.3 CMPSS Illustrative Graphs
    11. 7.11 Control Peripherals
      1. 7.11.1 Enhanced Capture (eCAP)
        1. 7.11.1.1 eCAP Electrical Data and Timing
          1. 7.11.1.1.1 eCAP Timing Requirements
          2. 7.11.1.1.2 eCAP Switching Characteristics
      2. 7.11.2 High-Resolution Capture Submodule (HRCAP6–HRCAP7)
        1. 7.11.2.1 HRCAP Electrical Data and Timing
          1. 7.11.2.1.1 HRCAP Switching Characteristics
      3. 7.11.3 Enhanced Pulse Width Modulator (ePWM)
        1. 7.11.3.1 Control Peripherals Synchronization
        2. 7.11.3.2 ePWM Electrical Data and Timing
          1. 7.11.3.2.1 ePWM Timing Requirements
          2. 7.11.3.2.2 ePWM Switching Characteristics
          3. 7.11.3.2.3 Trip-Zone Input Timing
            1. 7.11.3.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.11.3.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.11.3.3.1 External ADC Start-of-Conversion Switching Characteristics
      4. 7.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.11.4.1 HRPWM Electrical Data and Timing
          1. 7.11.4.1.1 High-Resolution PWM Characteristics
      5. 7.11.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.11.5.1 eQEP Electrical Data and Timing
          1. 7.11.5.1.1 eQEP Timing Requirements
          2. 7.11.5.1.2 eQEP Switching Characteristics
      6. 7.11.6 Sigma-Delta Filter Module (SDFM)
        1. 7.11.6.1 SDFM Electrical Data and Timing
          1. 7.11.6.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
          2. 7.11.6.1.2 SDFM Timing Diagram
        2. 7.11.6.2 SDFM Electrical Data and Timing (Synchronized GPIO)
          1. 7.11.6.2.1 SDFM Timing Requirements When Using Synchronized GPIO (SYNC) Option
    12. 7.12 Communications Peripherals
      1. 7.12.1 Controller Area Network (CAN)
      2. 7.12.2 Inter-Integrated Circuit (I2C)
        1. 7.12.2.1 I2C Electrical Data and Timing
          1. 7.12.2.1.1 I2C Timing Requirements
          2. 7.12.2.1.2 I2C Switching Characteristics
          3. 7.12.2.1.3 I2C Timing Diagram
      3. 7.12.3 Power Management Bus (PMBus) Interface
        1. 7.12.3.1 PMBus Electrical Data and Timing
          1. 7.12.3.1.1 PMBus Electrical Characteristics
          2. 7.12.3.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.12.3.1.3 PMBus Standard Mode Switching Characteristics
      4. 7.12.4 Serial Communications Interface (SCI)
      5. 7.12.5 Serial Peripheral Interface (SPI)
        1. 7.12.5.1 SPI Electrical Data and Timing
          1. 7.12.5.1.1 Non-High-Speed Master Mode Timings
            1. 7.12.5.1.1.1 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            2. 7.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            3. 7.12.5.1.1.3 SPI Master Mode Timing Requirements
          2. 7.12.5.1.2 Non-High-Speed Slave Mode Timings
            1. 7.12.5.1.2.1 SPI Slave Mode Switching Characteristics
            2. 7.12.5.1.2.2 SPI Slave Mode Timing Requirements
          3. 7.12.5.1.3 High-Speed Master Mode Timings
            1. 7.12.5.1.3.1 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
            2. 7.12.5.1.3.2 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
            3. 7.12.5.1.3.3 SPI High-Speed Master Mode Timing Requirements
          4. 7.12.5.1.4 High-Speed Slave Mode Timings
            1. 7.12.5.1.4.1 SPI High-Speed Slave Mode Switching Characteristics
            2. 7.12.5.1.4.2 SPI High-Speed Slave Mode Timing Requirements
      6. 7.12.6 Local Interconnect Network (LIN)
      7. 7.12.7 Fast Serial Interface (FSI)
        1. 7.12.7.1 FSI Transmitter
          1. 7.12.7.1.1 FSITX Electrical Data and Timing
            1. 7.12.7.1.1.1 FSITX Switching Characteristics
        2. 7.12.7.2 FSI Receiver
          1. 7.12.7.2.1 FSIRX Electrical Data and Timing
            1. 7.12.7.2.1.1 FSIRX Switching Characteristics
            2. 7.12.7.2.1.2 FSIRX Timing Requirements
        3. 7.12.7.3 FSI SPI Compatibility Mode
          1. 7.12.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.12.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Memory
      1. 8.3.1 C28x Memory Map
      2. 8.3.2 Control Law Accelerator (CLA) ROM Memory Map
      3. 8.3.3 Flash Memory Map
      4. 8.3.4 Peripheral Registers Memory Map
      5. 8.3.5 Memory Types
        1. 8.3.5.1 Dedicated RAM (Mx RAM)
        2. 8.3.5.2 Local Shared RAM (LSx RAM)
        3. 8.3.5.3 Global Shared RAM (GSx RAM)
        4. 8.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 8.4  Identification
    5. 8.5  Bus Architecture – Peripheral Connectivity
    6. 8.6  C28x Processor
      1. 8.6.1 Embedded Real-Time Analysis and Diagnostic (ERAD)
      2. 8.6.2 Floating-Point Unit (FPU)
      3. 8.6.3 Trigonometric Math Unit (TMU)
      4. 8.6.4 Viterbi, Complex Math and CRC Unit (VCU-I)
    7. 8.7  Control Law Accelerator (CLA)
    8. 8.8  Direct Memory Access (DMA)
    9. 8.9  Boot ROM and Peripheral Booting
      1. 8.9.1 Configuring Alternate Boot Mode Select Pins
      2. 8.9.2 Configuring Alternate Boot Mode Options
      3. 8.9.3 GPIO Assignments
    10. 8.10 Dual Code Security Module
    11. 8.11 Watchdog
    12. 8.12 Configurable Logic Block (CLB)
    13. 8.13 Functional Safety
  9. 9 Applications, Implementation, and Layout
    1. 9.1 Key Device Features
    2. 9.2 Application Information
      1. 9.2.1 Typical Application
        1. 9.2.1.1 Server Telecom Power Supply Unit (PSU)
          1. 9.2.1.1.1 System Block Diagram
          2. 9.2.1.1.2 Server and Telecom PSU Resources
        2. 9.2.1.2 Single-Phase Online UPS
          1. 9.2.1.2.1 System Block Diagram
          2. 9.2.1.2.2 Single phase online UPS Resources
        3. 9.2.1.3 Solar Micro Inverter
          1. 9.2.1.3.1 System Block Diagram
          2. 9.2.1.3.2 Solar Micro Inverter Resources
        4. 9.2.1.4 EV Charging Station Power Module
          1. 9.2.1.4.1 System Block Diagram
          2. 9.2.1.4.2 EV charging station power module Resources
        5. 9.2.1.5 Servo Drive Control Module
          1. 9.2.1.5.1 System Block Diagram
          2. 9.2.1.5.2 Servo Drive Control Module Resources
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Markings
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

6.4.1 GPIO Muxed Pins

The GPIO Muxed Pins table lists the GPIO muxed pins. The default mode for each GPIO pin is the GPIO function, except GPIO35 and GPIO37, which default to TDI and TDO, respectively. Secondary functions can be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be configured before the GPyMUXn to avoid transient pulses on GPIOs from alternate mux selections. Columns that are not shown and blank cells are reserved GPIO Mux settings.

Note:

GPIO20, GPIO21, and GPIO41 to GPIO55 are not available on any packages. Boot ROM enables pullups on these pins. For more details, see Section 6.5.

Table 6-6 GPIO Muxed Pins
0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15
GPIO0 EPWM1_A I2CA_SDA
GPIO1 EPWM1_B I2CA_SCL
GPIO2 EPWM2_A OUTPUTXBAR1 PMBUSA_SDA SCIA_TX FSIRXA_D1
GPIO3 EPWM2_B OUTPUTXBAR2 OUTPUTXBAR2 PMBUSA_SCL SPIA_CLK SCIA_RX FSIRXA_D0
GPIO4 EPWM3_A OUTPUTXBAR3 CANA_TX FSIRXA_CLK
GPIO5 EPWM3_B OUTPUTXBAR3 CANA_RX SPIA_STE FSITXA_D1
GPIO6 EPWM4_A OUTPUTXBAR4 SYNCOUT EQEP1_A CANB_TX SPIB_SOMI FSITXA_D0
GPIO7 EPWM4_B OUTPUTXBAR5 EQEP1_B CANB_RX SPIB_SIMO FSITXA_CLK
GPIO8 EPWM5_A CANB_TX ADCSOCAO EQEP1_STROBE SCIA_TX SPIA_SIMO I2CA_SCL FSITXA_D1
GPIO9 EPWM5_B SCIB_TX OUTPUTXBAR6 EQEP1_INDEX SCIA_RX SPIA_CLK FSITXA_D0
GPIO10 EPWM6_A CANB_RX ADCSOCBO EQEP1_A SCIB_TX SPIA_SOMI I2CA_SDA FSITXA_CLK
GPIO11 EPWM6_B SCIB_RX OUTPUTXBAR7 EQEP1_B SCIB_RX SPIA_STE FSIRXA_D1
GPIO12 EPWM7_A CANB_TX EQEP1_STROBE SCIB_TX PMBUSA_CTL FSIRXA_D0
GPIO13 EPWM7_B CANB_RX EQEP1_INDEX SCIB_RX PMBUSA_ALERT FSIRXA_CLK
GPIO14 EPWM8_A SCIB_TX OUTPUTXBAR3 PMBUSA_SDA SPIB_CLK EQEP2_A
GPIO15 EPWM8_B SCIB_RX OUTPUTXBAR4 PMBUSA_SCL SPIB_STE EQEP2_B
GPIO16 SPIA_SIMO CANB_TX OUTPUTXBAR7 EPWM5_A SCIA_TX SD1_D1 EQEP1_STROBE PMBUSA_SCL XCLKOUT
GPIO17 SPIA_SOMI CANB_RX OUTPUTXBAR8 EPWM5_B SCIA_RX SD1_C1 EQEP1_INDEX PMBUSA_SDA
GPIO18_X2 SPIA_CLK SCIB_TX CANA_RX EPWM6_A I2CA_SCL SD1_D2 EQEP2_A PMBUSA_CTL XCLKOUT
GPIO20
GPIO21
GPIO22_VFBSW EQEP1_STROBE SCIB_TX SPIB_CLK SD1_D4 LINA_TX
GPIO23_VSW
GPIO24 OUTPUTXBAR1 EQEP2_A EPWM8_A SPIB_SIMO SD1_D1 PMBUSA_SCL SCIA_TX ERRORSTS
GPIO25 OUTPUTXBAR2 EQEP2_B SPIB_SOMI SD1_C1 FSITXA_D1 PMBUSA_SDA SCIA_RX
GPIO26 OUTPUTXBAR3 EQEP2_INDEX OUTPUTXBAR3 SPIB_CLK SD1_D2 FSITXA_D0 PMBUSA_CTL I2CA_SDA
GPIO27 OUTPUTXBAR4 EQEP2_STROBE OUTPUTXBAR4 SPIB_STE SD1_C2 FSITXA_CLK PMBUSA_ALERT I2CA_SCL
GPIO28 SCIA_RX EPWM7_A OUTPUTXBAR5 EQEP1_A SD1_D3 EQEP2_STROBE LINA_TX SPIB_CLK ERRORSTS
GPIO29 SCIA_TX EPWM7_B OUTPUTXBAR6 EQEP1_B SD1_C3 EQEP2_INDEX LINA_RX SPIB_STE ERRORSTS
GPIO30 CANA_RX SPIB_SIMO OUTPUTXBAR7 EQEP1_STROBE SD1_D4
GPIO31 CANA_TX SPIB_SOMI OUTPUTXBAR8 EQEP1_INDEX SD1_C4 FSIRXA_D1
GPIO32 I2CA_SDA SPIB_CLK EPWM8_B LINA_TX SD1_D3 FSIRXA_D0 CANA_TX
GPIO33 I2CA_SCL SPIB_STE OUTPUTXBAR4 LINA_RX SD1_C3 FSIRXA_CLK CANA_RX
GPIO34 OUTPUTXBAR1 PMBUSA_SDA
GPIO35 SCIA_RX I2CA_SDA CANA_RX PMBUSA_SCL LINA_RX EQEP1_A PMBUSA_CTL TDI
GPIO37 OUTPUTXBAR2 I2CA_SCL SCIA_TX CANA_TX LINA_TX EQEP1_B PMBUSA_ALERT TDO
GPIO39 CANB_RX FSIRXA_CLK
GPIO40 PMBUSA_SDA FSIRXA_D0 SCIB_TX EQEP1_A
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56 SPIA_CLK EQEP2_STROBE SCIB_TX SD1_D3 SPIB_SIMO EQEP1_A
GPIO57 SPIA_STE EQEP2_INDEX SCIB_RX SD1_C3 SPIB_SOMI EQEP1_B
GPIO58 OUTPUTXBAR1 SPIB_CLK SD1_D4 LINA_TX CANB_TX EQEP1_STROBE
GPIO59 OUTPUTXBAR2 SPIB_STE SD1_C4 LINA_RX CANB_RX EQEP1_INDEX

The Digital Signals by GPIO table lists all muxed signals available and the respective GPIO within each package.

Table 6-7 Digital Signals by GPIO
SIGNAL NAMEPIN TYPEDESCRIPTION100 PZ64 PMQ64 PM56 RSH
ADCSOCAOOADC Start of Conversion A Output for External ADC (from ePWM modules)GPIO8GPIO8GPIO8GPIO8
ADCSOCBOOADC Start of Conversion B Output for External ADC (from ePWM modules)GPIO10GPIO10GPIO10
CANA_RXICAN-A ReceiveGPIO5
GPIO18_X2
GPIO30
GPIO33
GPIO35/TDI		GPIO5
GPIO18_X2
GPIO33
GPIO35/TDI		GPIO5
GPIO18_X2
GPIO33
GPIO35/TDI		GPIO5
GPIO18_X2
GPIO33
GPIO35/TDI
CANA_TXOCAN-A TransmitGPIO4
GPIO31
GPIO32
GPIO37/TDO		GPIO4
GPIO32
GPIO37/TDO		GPIO4
GPIO32
GPIO37/TDO		GPIO4
GPIO32
GPIO37/TDO
CANB_RXICAN-B ReceiveGPIO7
GPIO10
GPIO13
GPIO17
GPIO39
GPIO59		GPIO7
GPIO10
GPIO17		GPIO7
GPIO10
GPIO13
GPIO17		GPIO7
GPIO13
GPIO17
CANB_TXOCAN-B TransmitGPIO6
GPIO8
GPIO12
GPIO16
GPIO58		GPIO6
GPIO8
GPIO16		GPIO6
GPIO8
GPIO12
GPIO16		GPIO6
GPIO8
GPIO12
GPIO16
EPWM1_AOePWM-1 Output AGPIO0GPIO0GPIO0GPIO0
EPWM1_BOePWM-1 Output BGPIO1GPIO1GPIO1GPIO1
EPWM2_AOePWM-2 Output AGPIO2GPIO2GPIO2GPIO2
EPWM2_BOePWM-2 Output BGPIO3GPIO3GPIO3GPIO3
EPWM3_AOePWM-3 Output AGPIO4GPIO4GPIO4GPIO4
EPWM3_BOePWM-3 Output BGPIO5GPIO5GPIO5GPIO5
EPWM4_AOePWM-4 Output AGPIO6GPIO6GPIO6GPIO6
EPWM4_BOePWM-4 Output BGPIO7GPIO7GPIO7GPIO7
EPWM5_AOePWM-5 Output AGPIO8
GPIO16		GPIO8
GPIO16		GPIO8
GPIO16		GPIO8
GPIO16
EPWM5_BOePWM-5 Output BGPIO9
GPIO17		GPIO9
GPIO17		GPIO9
GPIO17		GPIO9
GPIO17
EPWM6_AOePWM-6 Output AGPIO10
GPIO18_X2		GPIO10
GPIO18_X2		GPIO10
GPIO18_X2		GPIO18_X2
EPWM6_BOePWM-6 Output BGPIO11GPIO11GPIO11GPIO11
EPWM7_AOePWM-7 Output AGPIO12
GPIO28		GPIO28GPIO12
GPIO28		GPIO12
GPIO28
EPWM7_BOePWM-7 Output BGPIO13
GPIO29		GPIO29GPIO13
GPIO29		GPIO13
GPIO29
EPWM8_AOePWM-8 Output AGPIO14
GPIO24		GPIO24GPIO24GPIO24
EPWM8_BOePWM-8 Output BGPIO15
GPIO32		GPIO32GPIO32GPIO32
EQEP1_AIeQEP-1 Input AGPIO6
GPIO10
GPIO28
GPIO35/TDI
GPIO40
GPIO56		GPIO6
GPIO10
GPIO28
GPIO35/TDI		GPIO6
GPIO10
GPIO28
GPIO35/TDI		GPIO6
GPIO28
GPIO35/TDI
EQEP1_BIeQEP-1 Input BGPIO7
GPIO11
GPIO29
GPIO37/TDO
GPIO57		GPIO7
GPIO11
GPIO29
GPIO37/TDO		GPIO7
GPIO11
GPIO29
GPIO37/TDO		GPIO7
GPIO11
GPIO29
GPIO37/TDO
EQEP1_INDEXI/OeQEP-1 IndexGPIO9
GPIO13
GPIO17
GPIO31
GPIO59		GPIO9
GPIO17		GPIO9
GPIO13
GPIO17		GPIO9
GPIO13
GPIO17
EQEP1_STROBEI/OeQEP-1 StrobeGPIO8
GPIO12
GPIO16
GPIO22_VFBSW
GPIO30
GPIO58		GPIO8
GPIO16
GPIO22_VFBSW		GPIO8
GPIO12
GPIO16
GPIO22_VFBSW		GPIO8
GPIO12
GPIO16
GPIO22_VFBSW
EQEP2_AIeQEP-2 Input AGPIO14
GPIO18_X2
GPIO24		GPIO18_X2
GPIO24		GPIO18_X2
GPIO24		GPIO18_X2
GPIO24
EQEP2_BIeQEP-2 Input BGPIO15
GPIO25
EQEP2_INDEXI/OeQEP-2 IndexGPIO26
GPIO29
GPIO57		GPIO29GPIO29GPIO29
EQEP2_STROBEI/OeQEP-2 StrobeGPIO27
GPIO28
GPIO56		GPIO28GPIO28GPIO28
ERRORSTSOActive-low Error Status Output. If you want an error state to be asserted during power up or during a fault with the ERRORSTS signal itself, an external pulldown resistor may be used. A pullup resistor may be used if you do not want an error state asserted for the conditions mentioned. GPIO24
GPIO28
GPIO29		GPIO24
GPIO28
GPIO29		GPIO24
GPIO28
GPIO29		GPIO24
GPIO28
GPIO29
FSIRXA_CLKIFSIRX-A Input ClockGPIO4
GPIO13
GPIO33
GPIO39		GPIO4
GPIO33		GPIO4
GPIO13
GPIO33		GPIO4
GPIO13
GPIO33
FSIRXA_D0IFSIRX-A Primary Data InputGPIO3
GPIO12
GPIO32
GPIO40		GPIO3
GPIO32		GPIO3
GPIO12
GPIO32		GPIO3
GPIO12
GPIO32
FSIRXA_D1IFSIRX-A Optional Additional Data InputGPIO2
GPIO11
GPIO31		GPIO2
GPIO11		GPIO2
GPIO11		GPIO2
GPIO11
FSITXA_CLKOFSITX-A Output ClockGPIO7
GPIO10
GPIO27		GPIO7
GPIO10		GPIO7
GPIO10		GPIO7
FSITXA_D0OFSITX-A Primary Data OutputGPIO6
GPIO9
GPIO26		GPIO6
GPIO9		GPIO6
GPIO9		GPIO6
GPIO9
FSITXA_D1OFSITX-A Optional Additional Data OutputGPIO5
GPIO8
GPIO25		GPIO5
GPIO8		GPIO5
GPIO8		GPIO5
GPIO8
I2CA_SCLI/ODI2C-A Open-Drain Bidirectional ClockGPIO1
GPIO8
GPIO18_X2
GPIO27
GPIO33
GPIO37/TDO		GPIO1
GPIO8
GPIO18_X2
GPIO33
GPIO37/TDO		GPIO1
GPIO8
GPIO18_X2
GPIO33
GPIO37/TDO		GPIO1
GPIO8
GPIO18_X2
GPIO33
GPIO37/TDO
I2CA_SDAI/ODI2C-A Open-Drain Bidirectional DataGPIO0
GPIO10
GPIO26
GPIO32
GPIO35/TDI		GPIO0
GPIO10
GPIO32
GPIO35/TDI		GPIO0
GPIO10
GPIO32
GPIO35/TDI		GPIO0
GPIO32
GPIO35/TDI
LINA_RXILIN-A ReceiveGPIO29
GPIO33
GPIO35/TDI
GPIO59		GPIO29
GPIO33
GPIO35/TDI		GPIO29
GPIO33
GPIO35/TDI		GPIO29
GPIO33
GPIO35/TDI
LINA_TXOLIN-A TransmitGPIO22_VFBSW
GPIO28
GPIO32
GPIO37/TDO
GPIO58		GPIO22_VFBSW
GPIO28
GPIO32
GPIO37/TDO		GPIO22_VFBSW
GPIO28
GPIO32
GPIO37/TDO		GPIO22_VFBSW
GPIO28
GPIO32
GPIO37/TDO
OUTPUTXBAR1OOutput X-BAR Output 1GPIO2
GPIO24
GPIO34
GPIO58		GPIO2
GPIO24		GPIO2
GPIO24		GPIO2
GPIO24
OUTPUTXBAR2OOutput X-BAR Output 2GPIO3
GPIO25
GPIO37/TDO
GPIO59		GPIO3
GPIO37/TDO		GPIO3
GPIO37/TDO		GPIO3
GPIO37/TDO
OUTPUTXBAR3OOutput X-BAR Output 3GPIO4
GPIO5
GPIO14
GPIO26		GPIO4
GPIO5		GPIO4
GPIO5		GPIO4
GPIO5
OUTPUTXBAR4OOutput X-BAR Output 4GPIO6
GPIO15
GPIO27
GPIO33		GPIO6
GPIO33		GPIO6
GPIO33		GPIO6
GPIO33
OUTPUTXBAR5OOutput X-BAR Output 5GPIO7
GPIO28		GPIO7
GPIO28		GPIO7
GPIO28		GPIO7
GPIO28
OUTPUTXBAR6OOutput X-BAR Output 6GPIO9
GPIO29		GPIO9
GPIO29		GPIO9
GPIO29		GPIO9
GPIO29
OUTPUTXBAR7OOutput X-BAR Output 7GPIO11
GPIO16
GPIO30		GPIO11
GPIO16		GPIO11
GPIO16		GPIO11
GPIO16
OUTPUTXBAR8OOutput X-BAR Output 8GPIO17
GPIO31		GPIO17GPIO17GPIO17
PMBUSA_ALERTI/ODPMBus-A Open-Drain Bidirectional Alert SignalGPIO13
GPIO27
GPIO37/TDO		GPIO37/TDOGPIO13
GPIO37/TDO		GPIO13
GPIO37/TDO
PMBUSA_CTLIPMBus-A Control SignalGPIO12
GPIO18_X2
GPIO26
GPIO35/TDI		GPIO18_X2
GPIO35/TDI		GPIO12
GPIO18_X2
GPIO35/TDI		GPIO12
GPIO18_X2
GPIO35/TDI
PMBUSA_SCLI/ODPMBus-A Open-Drain Bidirectional ClockGPIO3
GPIO15
GPIO16
GPIO24
GPIO35/TDI		GPIO3
GPIO16
GPIO24
GPIO35/TDI		GPIO3
GPIO16
GPIO24
GPIO35/TDI		GPIO3
GPIO16
GPIO24
GPIO35/TDI
PMBUSA_SDAI/ODPMBus-A Open-Drain Bidirectional DataGPIO2
GPIO14
GPIO17
GPIO25
GPIO34
GPIO40		GPIO2
GPIO17		GPIO2
GPIO17		GPIO2
GPIO17
SCIA_RXISCI-A Receive DataGPIO3
GPIO9
GPIO17
GPIO25
GPIO28
GPIO35/TDI		GPIO3
GPIO9
GPIO17
GPIO28
GPIO35/TDI		GPIO3
GPIO9
GPIO17
GPIO28
GPIO35/TDI		GPIO3
GPIO9
GPIO17
GPIO28
GPIO35/TDI
SCIA_TXOSCI-A Transmit DataGPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/TDO		GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/TDO		GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/TDO		GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/TDO
SCIB_RXISCI-B Receive DataGPIO11
GPIO13
GPIO15
GPIO57		GPIO11GPIO11
GPIO13		GPIO11
GPIO13
SCIB_TXOSCI-B Transmit DataGPIO9
GPIO10
GPIO12
GPIO14
GPIO18_X2
GPIO22_VFBSW
GPIO40
GPIO56		GPIO9
GPIO10
GPIO18_X2
GPIO22_VFBSW		GPIO9
GPIO10
GPIO12
GPIO18_X2
GPIO22_VFBSW		GPIO9
GPIO12
GPIO18_X2
GPIO22_VFBSW
SD1_C1ISDFM-1 Channel 1 Clock InputGPIO17
GPIO25		GPIO17GPIO17GPIO17
SD1_C2ISDFM-1 Channel 2 Clock InputGPIO27
SD1_C3ISDFM-1 Channel 3 Clock InputGPIO29
GPIO33
GPIO57		GPIO29
GPIO33		GPIO29
GPIO33		GPIO29
GPIO33
SD1_C4ISDFM-1 Channel 4 Clock InputGPIO31
GPIO59
SD1_D1ISDFM-1 Channel 1 Data InputGPIO16
GPIO24		GPIO16
GPIO24		GPIO16
GPIO24		GPIO16
GPIO24
SD1_D2ISDFM-1 Channel 2 Data InputGPIO18_X2
GPIO26		GPIO18_X2GPIO18_X2GPIO18_X2
SD1_D3ISDFM-1 Channel 3 Data InputGPIO28
GPIO32
GPIO56		GPIO28
GPIO32		GPIO28
GPIO32		GPIO28
GPIO32
SD1_D4ISDFM-1 Channel 4 Data InputGPIO22_VFBSW
GPIO30
GPIO58		GPIO22_VFBSWGPIO22_VFBSWGPIO22_VFBSW
SPIA_CLKI/OSPI-A ClockGPIO3
GPIO9
GPIO18_X2
GPIO56		GPIO3
GPIO9
GPIO18_X2		GPIO3
GPIO9
GPIO18_X2		GPIO3
GPIO9
GPIO18_X2
SPIA_SIMOI/OSPI-A Slave In, Master Out (SIMO)GPIO8
GPIO16		GPIO8
GPIO16		GPIO8
GPIO16		GPIO8
GPIO16
SPIA_SOMII/OSPI-A Slave Out, Master In (SOMI)GPIO10
GPIO17		GPIO10
GPIO17		GPIO10
GPIO17		GPIO17
SPIA_STEI/OSPI-A Slave Transmit Enable (STE)GPIO5
GPIO11
GPIO57		GPIO5
GPIO11		GPIO5
GPIO11		GPIO5
GPIO11
SPIB_CLKI/OSPI-B ClockGPIO14
GPIO22_VFBSW
GPIO26
GPIO28
GPIO32
GPIO58		GPIO22_VFBSW
GPIO28
GPIO32		GPIO22_VFBSW
GPIO28
GPIO32		GPIO22_VFBSW
GPIO28
GPIO32
SPIB_SIMOI/OSPI-B Slave In, Master Out (SIMO)GPIO7
GPIO24
GPIO30
GPIO56		GPIO7
GPIO24		GPIO7
GPIO24		GPIO7
GPIO24
SPIB_SOMII/OSPI-B Slave Out, Master In (SOMI)GPIO6
GPIO25
GPIO31
GPIO57		GPIO6GPIO6GPIO6
SPIB_STEI/OSPI-B Slave Transmit Enable (STE)GPIO15
GPIO27
GPIO29
GPIO33
GPIO59		GPIO29
GPIO33		GPIO29
GPIO33		GPIO29
GPIO33
SYNCOUTOExternal ePWM Synchronization PulseGPIO6GPIO6GPIO6GPIO6
TDIIJTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input.GPIO35/TDIGPIO35/TDIGPIO35/TDIGPIO35/TDI
TDOOJTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input.GPIO37/TDOGPIO37/TDOGPIO37/TDOGPIO37/TDO
VFBSW-Internal DC-DC regulator feedback signal. If the internal DC-DC regulator is used, tie this pin to the node where L(VSW) connects to the VDD rail (as close as possible to the device).GPIO22_VFBSWGPIO22_VFBSWGPIO22_VFBSWGPIO22_VFBSW
VSW-Switching output of the internal DC-DC regulatorGPIO23_VSWGPIO23_VSWGPIO23_VSWGPIO23_VSW
X2I/OCrystal oscillator outputGPIO18_X2GPIO18_X2GPIO18_X2GPIO18_X2
XCLKOUTOExternal Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.GPIO16
GPIO18_X2		GPIO16
GPIO18_X2		GPIO16
GPIO18_X2		GPIO16
GPIO18_X2