SPRSP14E may 2019 – june 2023 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
PRODUCTION DATA
SIGNAL NAME | DESCRIPTION | PIN TYPE | GPIO PIN | 337 BGA PIN | 176 Pin PIN |
---|---|---|---|---|---|
ERRORSTS | Error Status Output. When used, this signal requires an external pulldown. | O | U19 | 92 | |
FLT1 | Flash test pin 1. Reserved for TI. Must be left unconnected. | I/O | W12 | 73 | |
FLT2 | Flash test pin 2. Reserved for TI. Must be left unconnected. | I/O | V13 | 74 | |
NC1 | No Connection. This pin is not internally connected to the device. This pin may be left open or connected to any voltage within the maximum operating conditions. | H4 | |||
NC2 | No Connection. This pin is not internally connected in the device and may be left open or tied to VSS or VDDIO. NOTE: On other C2000 devices with an internal voltage regulator (VREG), this pin will be VREGENZ (internal voltage regulator enable). To enable PCB compatibility across C2000 devices this pin should be connected to VDDIO (3.3v). This will ensure the internal VREG, when present on other devices, would be disabled and not conflict with an external VREG which must be used with this device. | J18 | 119 | ||
TCK | JTAG test clock with internal pullup. | I | V15 | 81 | |
TDI | JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. | I | W13 | 77 | |
TDO | JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. | O | W15 | 78 | |
TMS | JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. An external pullup resistor (recommended 2.2 kΩ) on the TMS pin to VDDIO should be placed on the board to keep JTAG in reset during normal operation. | I | W14 | 80 | |
TRSTn |
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST must be maintained low at all times during normal device operation, so an external pulldown resistor is required on this pin for protection against noise spikes. The value of this resistor should be as small as possible, so long as the JTAG debug probe is still able to drive the TRST pin high. A resistor between 2.2 kΩ and 10 kΩ generally offers adequate protection. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debug probe and the application. This pin has an internal 50-ns (nominal) glitch filter. |
I | V14 | 79 | |
X1 | Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. | I | G19 | 123 | |
X2 | Crystal oscillator output. | O | J19 | 121 | |
XRSn | Device Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. The output buffer of this pin is an open-drain with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device. | I/OD | F19 | 124 |