SPRSP14E may 2019 – june 2023 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
PRODUCTION DATA
The receiver module interfaces to the FSI clock (RXCLK) and the data lines (RXD0 and RXD1) after they pass through the programmable delay line. The receiver core handles the data framing, CRC computation, and frame-related error checking. The receiver bit clock and state machine are run by the RXCLK input, which is asynchronous to the device system clock.
The receiver control registers let the CPU (or the CLA) program, control, and monitor the operation of the FSIRX. The receive data buffer is accessible by the CPU, CLA, and the DMA.
The receiver core has the following features:
Figure 7-69 shows the FSIRX CPU interface. Figure 7-70 provides a high-level overview of the internal modules present in the FSIRX. Not all data paths and internal connections are shown.