SPRSP35K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
OUTPUT CONDITIONS | ||||
CL | Output load capacitance | 2 | 5 | pF |
PCB CONNECTIVITY REQUIREMENTS | ||||
td(Trace Mismatch) | Propagation delay mismatch across all traces | 200 | ps |
Table 6-102 and Figure 6-121 assume testing over the recommended operating conditions and electrical characteristic conditions.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1.8 V Mode | |||||
DBTR1 | tc(TRC_CLK) | Cycle time, TRC_CLK | 6.50 | ns | |
DBTR2 | tw(TRC_CLKH) | Pulse width, TRC_CLK high | 2.50 | ns | |
DBTR3 | tw(TRC_CLKL) | Pulse width, TRC_CLK low | 2.50 | ns | |
DBTR4 | tosu(TRC_DATAV-TRC_CLK) | Output setup time, TRC_DATA valid to TRC_CLK edge | 0.81 | ns | |
DBTR5 | toh(TRC_CLK-TRC_DATAI) | Output hold time, TRC_CLK edge to TRC_DATA invalid | 0.81 | ns | |
DBTR6 | tosu(TRC_CTLV-TRC_CLK) | Output setup time, TRC_CTL valid to TRC_CLK edge | 0.81 | ns | |
DBTR7 | toh(TRC_CLK-TRC_CTLI) | Output hold time, TRC_CLK edge to TRC_CTL invalid | 0.81 | ns | |
3.3 V Mode | |||||
DBTR1 | tc(TRC_CLK) | Cycle time, TRC_CLK | 9.75 | ns | |
DBTR2 | tw(TRC_CLKH) | Pulse width, TRC_CLK high | 4.13 | ns | |
DBTR3 | tw(TRC_CLKL) | Pulse width, TRC_CLK low | 4.13 | ns | |
DBTR4 | tosu(TRC_DATAV-TRC_CLK) | Output setup time, TRC_DATA valid to TRC_CLK edge | 1.22 | ns | |
DBTR5 | toh(TRC_CLK-TRC_DATAI) | Output hold time, TRC_CLK edge to TRC_DATA invalid | 1.22 | ns | |
DBTR6 | tosu(TRC_CTLV-TRC_CLK) | Output setup time, TRC_CTL valid to TRC_CLK edge | 1.22 | ns | |
DBTR7 | toh(TRC_CLK-TRC_CTLI) | Output hold time, TRC_CLK edge to TRC_CTL invalid | 1.22 | ns |