SPRSP35 Data sheet

SPRSP35K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1

PRODUCTION DATA

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

PARAMETER			MIN	MAX	UNIT
VDD_CORE	MAIN domain core supply		–0.3	1.05	V
VDD_MCU	MCUSS core supply		–0.3	1.05	V
VDD_CPU	CPU core supply		–0.3	1.05	V
VDDA_0P8_DLL_MMC0	MMC0 DLL analog supply		–0.3	1.05	V
VDDAR_CORE	MAIN domain RAM supply		–0.3	1.05	V
VDDAR_MCU	MCUSS RAM supply		–0.3	1.05	V
VDDAR_CPU	CPU RAM supply		–0.3	1.05	V
VDDA_0P8_DP	Displayport SERDES analog supply low		–0.3	1.05	V
VDDA_0P8_DP_C	Displayport SERDES clock supply		–0.3	1.05	V
VDDA_0P8_DSITX	DSITX clock supply		–0.3	1.05	V
VDDA_0P8_DSITX_C	DSITX clock supply		–0.3	1.05	V
VDDA_0P8_CSIRX	CSIRX analog supply low		–0.3	1.05	V
VDDA_0P8_SERDES0_1	SERDES0-1 analog supply low		–0.3	1.05	V
VDDA_0P8_SERDES2_3	SERDES2-3 analog supply low		–0.3	1.05	V
VDDA_0P8_SERDES_C0_1	SERDES0-1 clock supply		–0.3	1.05	V
VDDA_0P8_SERDES_C2_3	SERDES2-3 clock supply		–0.3	1.05	V
VDDA_0P8_USB	USB0-1 0.8 V analog supply		–0.3	1.05	V
VDDA_0P8_UFS	UFS analog supply low		–0.3	1.05	V
VDDA_0P8_PLL_MLB	MLB PLL analog supply		–0.3	1.05	V
VDDA_0P8_PLL_DDR	DDR PLL analog supply		–0.3	1.05	V
VDDA_1P8_USB	USB0-1 1.8 V analog supply		–0.3	2.2	V
VDDA_1P8_UFS	UFS analog supply high		–0.3	2.2	V
VDDA_1P8_DP	Displayport SERDES analog supply high		–0.3	2.2	V
VDDA_1P8_DSITX	DSITX analog supply high		–0.3	2.2	V
VDDA_1P8_CSIRX	CSIRX analog supply high		–0.3	2.2	V
VDDA_1P8_SERDES0_1	SERDES0-1 analog supply high		–0.3	2.2	V
VDDA_1P8_SERDES2_3	SERDES2-3 analog supply high		–0.3	2.2	V
VDDA_3P3_USB	USB0-1 3.3 V analog supply		–0.3	3.8	V
VDDA_MCU_PLLGRP0	Analog supply for MCU PLL Group 0		–0.3	2.2	V
VDDA_PLLGRP0	Analog supply for Main PLL Group 0		–0.3	2.2	V
VDDA_PLLGRP1	Analog supply for Main PLL Group 1		–0.3	2.2	V
VDDA_PLLGRP2	Analog supply for Main PLL Group 2		–0.3	2.2	V
VDDA_PLLGRP3	Analog supply for Main PLL Group 3		–0.3	2.2	V
VDDA_PLLGRP4	Analog supply for Main PLL Group 4		–0.3	2.2	V
VDDA_PLLGRP5	Analog supply for MAIN PLL Group 5 (DDR)		–0.3	2.2	V
VDDA_PLLGRP6	Analog supply for MAIN PLL Group 6		–0.3	2.2	V
VDDA_WKUP	Oscillator supply for WKUP domain		–0.3	2.2	V
VDDA_ADC0	ADC analog supply		–0.3	2.2	V
VDDA_ADC1	ADC analog supply		–0.3	2.2	V
VDDA_MCU_TEMP	Analog supply for temperature sensor 0 in MCU domain		–0.3	2.2	V
VDDA_POR_WKUP	WKUP domain analog supply		–0.3	2.2	V
VDDA_1P8_MLB	MLB IO supply (6-pin interface)		–0.3	2.2	V
VDDA_TEMP_0_1	Analog supply for temperature sensor 0		–0.3	2.2	V
VDDA_TEMP_2_3	Analog supply for temperature sensor 2		–0.3	2.2	V
VDDS_DDR	DDR inteface power supply		–0.3	1.2	V
VDDS_DDR_BIAS	Bias supply for LPDDR4		–0.3	1.2	V
VDDS_DDR_C	IO power for DDR Memory Clock Bit (MCB) macro		–0.3	1.2	V
VDDS_MMC0	MMC0 IO supply		–0.3	2.2	V
VDDS_OSC1	HFOSC1 supply		–0.3	2.2	V
VDDSHV0_MCU	IO supply MCUSS general IO group, and MCU and MAIN domain warm reset pins	1.8 V	–0.3	2.2	V
VDDSHV0_MCU		3.3 V	–0.3	3.8	V
VDDSHV0	IO supply for MAIN domain general	1.8 V	–0.3	2.2	V
VDDSHV0	IO supply for MAIN domain general	3.3 V	–0.3	3.8	V
VDDSHV1_MCU	IO supply for MCUSS IO group 1	1.8 V	–0.3	2.2	V
VDDSHV1_MCU	IO supply for MCUSS IO group 1	3.3 V	–0.3	3.8	V
VDDSHV1	IO supply for MAIN domain IO group 1	1.8 V	–0.3	2.2	V
VDDSHV1	IO supply for MAIN domain IO group 1	3.3 V	–0.3	3.8	V
VDDSHV2_MCU	IO supply for MCUSS IO group 2	1.8 V	–0.3	2.2	V
VDDSHV2_MCU	IO supply for MCUSS IO group 2	3.3 V	–0.3	3.8	V
VDDSHV2	IO supply for MAIN domain IO group 2	1.8 V	–0.3	2.2	V
VDDSHV2	IO supply for MAIN domain IO group 2	3.3 V	–0.3	3.8	V
VDDSHV3	IO supply for MAIN domain IO group 3	1.8 V	–0.3	2.2	V
VDDSHV3	IO supply for MAIN domain IO group 3	3.3 V	–0.3	3.8	V
VDDSHV4	IO supply for MAIN domain IO group 4	1.8 V	–0.3	2.2	V
VDDSHV4	IO supply for MAIN domain IO group 4	3.3 V	–0.3	3.8	V
VDDSHV5	IO supply for MAIN domain IO group 5	1.8 V	–0.3	2.2	V
VDDSHV5	IO supply for MAIN domain IO group 5	3.3 V	–0.3	3.8	V
VDDSHV6	IO supply for MAIN domain IO group 6	1.8 V	–0.3	2.2	V
VDDSHV6	IO supply for MAIN domain IO group 6	3.3 V	–0.3	3.8	V
VPP_CORE	Supply voltage range for CORE EFUSE domain		–0.3	1.89	V
VPP_MCU	Supply voltage range for MCU EFUSE domain		–0.3	1.89	V
USB0_VBUS⁽⁹⁾	Voltage range for USB VBUS comparator input		–0.3	3.6	V
USB1_VBUS⁽⁹⁾	Voltage range for USB VBUS comparator input		–0.3	3.6	V
Steady State Max. Voltage at all fail-safe IO pins		I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA, MCU_I2C0_SCL, MCU_I2C0_SDA, EXTINTn	–0.3	3.8	V
		MCU_PORz, PORz	–0.3	3.8	V
		VMON_IR_VEXT	–0.3	2.2	V
		VMON_ER_VSYS⁽⁷⁾⁽⁸⁾	–0.3	1.05	V
Steady State Max. Voltage at all other IO pins⁽³⁾		All other IO pins	–0.3	IO supply voltage + 0.3	V
Transient Overshoot and Undershoot specification at IO pin		20% of IO supply voltage for up to 20% of signal period (see Figure 6-1, IO Transient Voltage Ranges)		0.2 × VDD⁽⁶⁾	V
Latch-up Performance, Class II (125°C)⁽⁴⁾		I-Test	–100	100	mA
Latch-up Performance, Class II (125°C)⁽⁴⁾		Over-Voltage (OV) Test	NA	1.5 × VDD⁽⁶⁾	V
T_STG⁽⁵⁾		Storage temperature	–55	+150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.4, Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted.

(3) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be –0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences.

(4) For current pulse injection:
Pins stressed per JEDEC JESD78E (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
For overvoltage performance:
Supplies stressed per JEDEC JESD78E (Class II) and passed specified voltage injection.

(5) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning to ambient room temperature before usage.

(6) VDD is the voltage on the corresponding power-supply pin(s) for the IO.

(7) An external resistor divider is required to create the VMON input value that triggers with V_TH = 0.45 when the V_SYS level reaches the minimum allowed threshold. A series resistor R2 (VMON_ER_VSYS = V_SYS × R1 / (R1 + R2)) of at least 10kΩ is recommended to limit current.

(8) The VMON_ER_VSYS pin provides a way to monitor the system power supply. For more information, see Section 8.3.5 System Power Supply Monitor Design Guidelines.

(9) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 8.3.4, USB VBUS Design Guidelines.

Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO power supplies are turned off. The I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, DDR_FS_RESETn, NMIn, VMON_ER_VSYS, and VMON_IR_VEXT are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section 6.1.

A. T_overshoot + T_undershoot < 20% of T_period

Figure 6-1 IO Transient Voltage Ranges