SPRSP35 Data sheet

SPRSP35K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1

PRODUCTION DATA

6.9.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode

NO.	PARAMETER	DESCRIPTION	MODE^⁽¹⁵⁾	MIN	MAX	UNIT
NO.	PARAMETER	DESCRIPTION	MODE^⁽¹⁵⁾	133 MHz^⁽¹⁶⁾		UNIT
FA0	t_w(be[x]nV)	Pulse duration, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid time	Read		N⁽¹²⁾	ns
FA0	t_w(be[x]nV)		Write		N⁽¹²⁾	ns
FA1	t_w(csnV)	Pulse duration, output chip select GPMC_CSn[i]⁽¹³⁾ low	Read		A⁽¹⁾	ns
FA1	t_w(csnV)	Pulse duration, output chip select GPMC_CSn[i]⁽¹³⁾ low	Write		A⁽¹⁾	ns
FA3	t_{d(csnV-advnIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output address valid and address latch enable GPMC_ADVn_ALE invalid	Read	B⁽²⁾-2.55	B⁽²⁾+2.65	ns
FA3	t_{d(csnV-advnIV)}		Write	B⁽²⁾-2.55	B⁽²⁾+2.65	ns
FA4	t_{d(csnV-oenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn invalid (Single read)	div_by_1_mode;	C⁽³⁾-2.55	C⁽³⁾+2.65	ns
FA9	t_d(aV-csnV)	Delay time, output address GPMC_A[27:1] valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	div_by_1_mode;	J⁽⁹⁾-2.55	J⁽⁹⁾+2.65	ns
FA10	t_{d(be[x]nV-csnV)}	Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	div_by_1_mode;	J⁽⁹⁾-2.55	J⁽⁹⁾+2.65	ns
FA12	t_{d(csnV-advnV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output address valid and address latch enable GPMC_ADVn_ALE valid	div_by_1_mode;	K⁽¹⁰⁾-2.55	K⁽¹⁰⁾+2.65	ns
FA13	t_d(csnV-oenV)	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn valid	div_by_1_mode;	L⁽¹¹⁾-2.55	L⁽¹¹⁾+2.65	ns
FA16	t_w(aIV)	Pulse duration output address GPMC_A[26:1] invalid between 2 successive read and write accesses	div_by_1_mode;	G⁽⁷⁾		ns
FA18	t_{d(csnV-oenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn invalid (Burst read)	div_by_1_mode;	I⁽⁸⁾-2.55	I⁽⁸⁾+2.65	ns
FA20	t_w(aV)	Pulse duration, output address GPMC_A[27:1] valid - 2nd, 3rd, and 4th accesses	div_by_1_mode;	D⁽⁴⁾		ns
FA25	t_d(csnV-wenV)	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output write enable GPMC_WEn valid	div_by_1_mode;	E⁽⁵⁾-2.55	E⁽⁵⁾+2.65	ns
FA27	t_{d(csnV-wenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output write enable GPMC_WEn invalid	div_by_1_mode;	F⁽⁶⁾-2.55	F⁽⁶⁾+2.65	ns
FA28	t_d(wenV-dV)	Delay time, output write enable GPMC_WEn valid to output data GPMC_AD[15:0] valid	div_by_1_mode;		2.65	ns
FA29	t_d(dV-csnV)	Delay time, output data GPMC_AD[15:0] valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	div_by_1_mode;	J⁽⁹⁾-2.55	J⁽⁹⁾+2.65	ns
FA37	t_d(oenV-aIV)	Delay time, output enable GPMC_OEn_REn valid to output address GPMC_AD[15:0] phase end	div_by_1_mode;		2.65	ns

(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
with n being the page burst access number

(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(7) G = Cycle2CycleDelay × GPMC_FCLK⁽¹⁴⁾

(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁴⁾

(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(15) For div_by_1_mode:

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
- GPMC_CLK frequency = GPMC_FCLK frequency

(16) For 133 MHz:

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT